Abstract: A k-bit data input and a 1-bit scan input of a scan flip-flop (21.sub.i) of a multiply-accumulation operation unit (4.sub.i) respectively receive a k-bit data output and a 1-bit scan output of a scan flip-flop (21.sub.i-1) of a multiply-accumulation operation unit (4.sub.j-1) in the previous stage. A j-bit data input and a 1-bit scan input of a scan flip-flop (22.sub.i) respectively receive a j-bit data output of an adder (3.sub.i-1) of a multiply-accumulation operation unit (4.sub.i-1)) in the previous stage and a 1-bit scan output of a scan flip-flop (22.sub.j+1) in the next stage.

Abstract: It is an object to obtain a multiplier circuit with reduced circuit scale or with reduced power consumption. Booth decoders (BD1-BD3) receive overlapping three bits of a 6-bit multiplier (Y) (Y0-Y5), respectively, and output partial product information groups (S1-S5) to partial product generating circuits (PP1-PP3) on the basis of the three bits of the multiplier (Y), respectively. Each partial product information is provided in a one-to-one correspondence for each kind of partial product. The partial product generating circuits (PP1-PP3) respectively receive the partial product information groups (S1-S5) from the respective Booth decoders (BD1-BD3) and a 8-bit multiplicand (X) (X0-X7), and output partial products (SM1-SM3) to a partial product adder circuit (ADD1). The partial product adder circuit (ADD1) adds the partial products (SM1-SM3) and outputs a multiplication result (XY) of the multiplier (Y) and the multiplicand (X).