Patents by Inventor Nobuhiro Nagura

Nobuhiro Nagura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10533169
    Abstract: A eukaryotic cell having xylose utilization ability. Provided is a protein that has xylose isomerase activity and has an amino acid sequence including, when aligned with an amino acid sequence expressed by SEQ ID NO:1, the 1st to 6th motifs expressed respectively by SEQ ID NOs:2 to 7 from the N-terminus side in the order described, and having, in place of asparagine (N) in an amino acid sequence of the 6th motif, another amino acid.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: January 14, 2020
    Assignees: KABUSHIKI KAISHA TOYOTA CHUO KENKYUSHO, TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Satoshi Katahira, Risa Nagura, Kenro Tokuhiro, Nobuhiro Ishida, Chie Imamura, Toru Onishi, Noriko Yasutani, Nobuki Tada
  • Patent number: 10410868
    Abstract: A semiconductor device includes a first nitride semiconductor layer formed over a substrate, a second nitride semiconductor layer formed over the first nitride semiconductor layer and having a band gap wider than a band gap of the first nitride semiconductor layer, a trench penetrating through the second nitride semiconductor layer and reaching an inside of the first nitride semiconductor layer, a gate electrode placed in the trench over a gate insulating film, and a first electrode and a second electrode formed over the second nitride semiconductor layer on both sides of the gate electrode, respectively.
    Type: Grant
    Filed: January 29, 2018
    Date of Patent: September 10, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Takashi Inoue, Tatsuo Nakayama, Yasuhiro Okamoto, Hiroshi Kawaguchi, Toshiyuki Takewaki, Nobuhiro Nagura, Takayuki Nagai, Yoshinao Miura, Hironobu Miyamoto
  • Publication number: 20180151377
    Abstract: A semiconductor device includes a first nitride semiconductor layer formed over a substrate, a second nitride semiconductor layer formed over the first nitride semiconductor layer and having a band gap wider than a band gap of the first nitride semiconductor layer, a trench penetrating through the second nitride semiconductor layer and reaching an inside of the first nitride semiconductor layer, a gate electrode placed in the trench over a gate insulating film, and a first electrode and a second electrode formed over the second nitride semiconductor layer on both sides of the gate electrode, respectively.
    Type: Application
    Filed: January 29, 2018
    Publication date: May 31, 2018
    Inventors: Takashi Inoue, Tatsuo Nakayama, Yasuhiro Okamoto, Hiroshi Kawaguchi, Toshiyuki Takewaki, Nobuhiro Nagura, Takayuki Nagai, Yoshinao Miura, Hironobu Miyamoto
  • Patent number: 9984884
    Abstract: A method of manufacturing a semiconductor device includes forming a first nitride semiconductor layer, forming thereover a second nitride semiconductor layer having a band gap wider than that of the first nitride semiconductor layer, and thereby forming a stacked body, etching the stacked body with a first film placed over the stacked body and including a first opening portion as a mask to form a trench penetrating through the second nitride semiconductor layer and reaching an inside of the first nitride semiconductor layer, causing an end portion of the first film to retreat from an end portion of the trench, forming a second film over the first film including the inside of the trench, and forming a gate electrode over the second film.
    Type: Grant
    Filed: December 20, 2016
    Date of Patent: May 29, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Takashi Inoue, Tatsuo Nakayama, Yasuhiro Okamoto, Hiroshi Kawaguchi, Toshiyuki Takewaki, Nobuhiro Nagura, Takayuki Nagai, Yoshinao Miura, Hironobu Miyamoto
  • Publication number: 20170103898
    Abstract: A method of manufacturing a semiconductor device includes forming a first nitride semiconductor layer, forming thereover a second nitride semiconductor layer having a band gap wider than that of the first nitride semiconductor layer, and thereby forming a stacked body, etching the stacked body with a first film placed over the stacked body and including a first opening portion as a mask to form a trench penetrating through the second nitride semiconductor layer and reaching an inside of the first nitride semiconductor layer, causing an end portion of the first film to retreat from an end portion of the trench, forming a second film over the first film including the inside of the trench, and forming a gate electrode over the second film.
    Type: Application
    Filed: December 20, 2016
    Publication date: April 13, 2017
    Inventors: Takashi INOUE, Tatsuo Nakayama, Yasuhiro Okamoto, Hiroshi Kawaguchi, Toshiyuki Takewaki, Nobuhiro Nagura, Takayuki Nagai, Yoshinao Miura, Hironobu Miyamoto
  • Patent number: 9559183
    Abstract: To provide a semiconductor device having improved characteristics. The semiconductor device has a substrate and thereon a buffer layer, a channel layer, a barrier layer, a trench penetrating therethrough and reaching the inside of the channel layer, a gate electrode placed in the trench via a gate insulating film, and drain and source electrodes on the barrier layer on both sides of the gate electrode. The gate insulating film has a first portion made of a first insulating film and extending from the end portion of the trench to the side of the drain electrode and a second portion made of first and second insulating films and placed on the side of the drain electrode relative to the first portion. The on resistance can be reduced by decreasing the thickness of the first portion at the end portion of the trench on the side of the drain electrode.
    Type: Grant
    Filed: May 6, 2014
    Date of Patent: January 31, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Takashi Inoue, Tatsuo Nakayama, Yasuhiro Okamoto, Hiroshi Kawaguchi, Toshiyuki Takewaki, Nobuhiro Nagura, Takayuki Nagai, Yoshinao Miura, Hironobu Miyamoto
  • Publication number: 20140353720
    Abstract: To provide a semiconductor device having improved characteristics. The semiconductor device has a substrate and thereon a buffer layer, a channel layer, a barrier layer, a trench penetrating therethrough and reaching the inside of the channel layer, a gate electrode placed in the trench via a gate insulating film, and drain and source electrodes on the barrier layer on both sides of the gate electrode. The gate insulating film has a first portion made of a first insulating film and extending from the end portion of the trench to the side of the drain electrode and a second portion made of first and second insulating films and placed on the side of the drain electrode relative to the first portion. The on resistance can be reduced by decreasing the thickness of the first portion at the end portion of the trench on the side of the drain electrode.
    Type: Application
    Filed: May 6, 2014
    Publication date: December 4, 2014
    Applicant: Renesas Electronics Corporation
    Inventors: Takashi Inoue, Tatsuo Nakayama, Yasuhiro Okamoto, Hiroshi Kawaguchi, Toshiyuki Takewaki, Nobuhiro Nagura, Takayuki Nagai, Yoshinao Miura, Hironobu Miyamoto
  • Publication number: 20060193977
    Abstract: In an complementary metal oxide semiconductor (CMOS) device, a silicon-on-insulator (SOI) substrate structure includes a support substrate, a p?-type semiconductor substrate, and an insulating layer sandwiched between the support substrate and the p?-type semiconductor substrate. An element-isolation layer is formed in the p?-type semiconductor substrate to reach the insulating layer, so that an n-type well region is defined and surrounded by the insulating layer and the element-isolation layer. A p-type MOS transistor is formed in the n-type well region, and an n-type MOS transistor is formed in the first conductivity type semiconductor substrate so as to be adjacent to the n-type well region.
    Type: Application
    Filed: February 28, 2006
    Publication date: August 31, 2006
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Nobuhiro Nagura
  • Patent number: 5965928
    Abstract: A semiconductor device is provided, which is able to suppress the capacitance lowering of the capacitor due to a voltage applied across the capacitor. The device includes a well formed in a semiconductor substrate of a first conductivity type. The well is of a second conductivity type opposite to the first conductivity type. A surface area of the well is divided into at least first and second parts. The first part is of the first conductivity type and the second part is of the second conductivity type. An insulating layer is formed on the well to be contacted with the first and second parts. An electrode is formed on the insulating layer and is located over the first and second parts. The capacitor formed by the well, the insulating layer, and the electrode is equivalent to a capacitor composed by a first subcapacitor including the first part and a second subcapacitor including the second part.
    Type: Grant
    Filed: April 17, 1997
    Date of Patent: October 12, 1999
    Assignee: NEC Corporation
    Inventor: Nobuhiro Nagura