Patents by Inventor Nobuhiro Nonogaki

Nobuhiro Nonogaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10198082
    Abstract: A position input device includes a coordinate system setting unit that uses position and orientation of the head of an operator in a first coordinate system to set a second coordinate system in a space including the operator, where a position on the face of the operator is designated as an origin, a transformation matrix calculation unit that calculates a transformation matrix from the first to the second coordinate system, a transformation matrix update unit that updates the transformation matrix according to a result obtained by transforming a coordinate indicating a position of the fingertip of the operator in the first coordinate system with the transformation matrix, and an indication straight line calculation unit that calculates a straight line passing through the origin of the second coordinate system and the position of the fingertip based on the transformation matrix and the position of the fingertip in the first coordinate system.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: February 5, 2019
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Nobuhiro Nonogaki
  • Patent number: 10142643
    Abstract: According to one embodiment, a marker generating method is provided. In the marker generating method, a value in a bit string is replaced with a signal pattern to generate a first signal pattern arrangement. The first signal pattern arrangement is divided into a first partial signal and a second partial signal. The first partial signal having a pattern cycle extended to a pattern cycle of the second partial signal is added to the second partial signal to generate a second signal pattern arrangement. A gradation of shading which indicates a signal of the second signal pattern arrangement is set.
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: November 27, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Nobuhiro Nonogaki
  • Patent number: 10013602
    Abstract: A feature vector extraction device includes a cell learning unit setting a plurality of cells representing a position and range for counting a feature vector of a target on the basis of a plurality of images containing a target for learning use. A normalizer selects two feature points from among three or more feature points which are set in an image and represent the target for learning use, and normalizes a size and direction of each of the feature points. A feature point calculator calculates a mean position and a variation from the relevant mean position for each of other feature points than the selected two feature points of the normalized feature points. A cell decision unit decides a position of each of the cells on the basis of the mean position and decides a size of the each of the cells on the basis of the variation.
    Type: Grant
    Filed: September 8, 2015
    Date of Patent: July 3, 2018
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Nobuhiro Nonogaki
  • Publication number: 20180075291
    Abstract: A method for carrying out a biometrics authentication includes detecting an object from a first image including the object, detecting feature points of the object in the detected object, generating a second image based on the feature points, wherein the second image is a normalized image of the object that is obtained by rotating and resizing the object in the first image, determining whether or not the object in the second image faces front, calculating a feature value of the object upon determining that the object in the normalized image faces front, and comparing the calculated feature value with a reference feature value for the biometrics authentication.
    Type: Application
    Filed: March 2, 2017
    Publication date: March 15, 2018
    Inventors: Guifen TIAN, Nobuhiro NONOGAKI
  • Publication number: 20170076166
    Abstract: According to one embodiment, a marker generating method is provided. In the marker generating method, a value in a bit string is replaced with a signal pattern to generate a first signal pattern arrangement. The first signal pattern arrangement is divided into a first partial signal and a second partial signal. The first partial signal having a pattern cycle extended to a pattern cycle of the second partial signal is added to the second partial signal to generate a second signal pattern arrangement. A gradation of shading which indicates a signal of the second signal pattern arrangement is set.
    Type: Application
    Filed: March 7, 2016
    Publication date: March 16, 2017
    Inventor: Nobuhiro Nonogaki
  • Publication number: 20170031450
    Abstract: A position input device includes a coordinate system setting unit that uses position and orientation of the head of an operator in a first coordinate system to set a second coordinate system in a space including the operator, where a position on the face of the operator is designated as an origin, a transformation matrix calculation unit that calculates a transformation matrix from the first to the second coordinate system, a transformation matrix update unit that updates the transformation matrix according to a result obtained by transforming a coordinate indicating a position of the fingertip of the operator in the first coordinate system with the transformation matrix, and an indication straight line calculation unit that calculates a straight line passing through the origin of the second coordinate system and the position of the fingertip based on the transformation matrix and the position of the fingertip in the first coordinate system.
    Type: Application
    Filed: March 4, 2016
    Publication date: February 2, 2017
    Inventor: Nobuhiro NONOGAKI
  • Publication number: 20160253570
    Abstract: A feature vector extraction device includes a cell learning unit setting a plurality of cells representing a position and range for counting a feature vector of a target on the basis of a plurality of images containing a target for learning use. A normalizer selects two feature points from among three or more feature points which are set in an image and represent the target for learning use, and normalizes a size and direction of each of the feature points. A feature point calculator calculates a mean position and a variation from the relevant mean position for each of other feature points than the selected two feature points of the normalized feature points. A cell decision unit decides a position of each of the cells on the basis of the mean position and decides a size of the each of the cells on the basis of the variation.
    Type: Application
    Filed: September 8, 2015
    Publication date: September 1, 2016
    Inventor: Nobuhiro NONOGAKI
  • Patent number: 9104636
    Abstract: A memory managing apparatus manages a memory shared by processors. The apparatus includes an allocator, an updater and a releaser. The allocator secures a memory area in the memory allocated to each processor based on a request of each processor and registers reference counters corresponding one-to-one to the processors. The updater adds 1 to a value of the reference counter corresponding to the processor managing the memory area when the memory area is allocated to each processor and subtracts 1 from the value of the reference counter corresponding to the processor managing the memory area when the memory area is released from the processor to which the memory area is allocated. The releaser releases the memory area from the processor to which the memory area is allocated when a sum of the values of the reference counters in the memory area updated by the updater is 0.
    Type: Grant
    Filed: February 15, 2011
    Date of Patent: August 11, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Nobuhiro Nonogaki
  • Patent number: 9002118
    Abstract: An image feature extraction device according to an embodiment includes a gradient image calculator generates intensity gradient data with respect to two different directions based on intensity data of image data; and a gradient count unit calculates a covariance matrix for each partial area obtained by dividing the image data based on the intensity gradient data. The image feature extraction device according to the embodiment further includes a feature data output unit calculates two parameters related to a major axis and a minor axis of an ellipse expressed by the covariance matrix, quantizes a range of the logarithms of the parameters for each of the partial area using a predetermined division number, and outputs a feature vector which contains a value only at a dimension corresponding to the quantized range different from the other dimensions.
    Type: Grant
    Filed: September 11, 2013
    Date of Patent: April 7, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Nobuhiro Nonogaki
  • Publication number: 20140286576
    Abstract: An image feature extraction device according to an embodiment includes a gradient image calculator generates intensity gradient data with respect to two different directions based on intensity data of image data; and a gradient count unit calculates a covariance matrix for each partial area obtained by dividing the image data based on the intensity gradient data. The image feature extraction device according to the embodiment further includes a feature data output unit calculates two parameters related to a major axis and a minor axis of an ellipse expressed by the covariance matrix, quantizes a range of the logarithms of the parameters for each of the partial area using a predetermined division number, and outputs a feature vector which contains a value only at a dimension corresponding to the quantized range different from the other dimensions.
    Type: Application
    Filed: September 11, 2013
    Publication date: September 25, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Nobuhiro NONOGAKI
  • Patent number: 8373711
    Abstract: An image processing apparatus has a memory in which a plurality of image processing commands are stored, a dependent information producing unit which produces dependent information in each image data block becoming a target image processing, the dependent information indicating a dependency relationship between image processing of the image data block and another processing, a dependency relationship solving unit which makes a determination of a practicable image processing based on the dependent information, the dependency relationship solving unit writing an image processing command of the practicable image processing in the memory, and a plurality of image processing units which read an image processing command stored in the memory, the image processing units performing the image processing to the image data block based on the image processing command.
    Type: Grant
    Filed: November 28, 2007
    Date of Patent: February 12, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takeshi Kodaka, Nobuhiro Nonogaki
  • Publication number: 20120327206
    Abstract: According to one embodiment, an information processing apparatus includes a camera, first and second feature region detectors, a plural operation command generators and a selector. The camera obtains an image of at least a part of a human body and generates image data of the obtained image. The first feature region detector detects a first feature region including a feature part of the human body from the image data and generates first feature region information defining the first feature region. The second feature region detector generates second feature region information defining a second feature region corresponding to the first feature region in a virtual space based on the first feature region information. The operation command generators generate operation commands corresponding to a plurality of partial spaces in the virtual space. The selector selects one of the operation command generators based on the second feature region information.
    Type: Application
    Filed: March 12, 2012
    Publication date: December 27, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Nobuhiro Nonogaki
  • Publication number: 20120102274
    Abstract: A memory managing apparatus manages a memory shared by processors. The apparatus includes an allocator, an updater and a releaser. The allocator secures a memory area in the memory allocated to each processor based on a request of each processor and registers reference counters corresponding one-to-one to the processors. The updater adds 1 to a value of the reference counter corresponding to the processor managing the memory area when the memory area is allocated to each processor and subtracts 1 from the value of the reference counter corresponding to the processor managing the memory area when the memory area is released from the processor to which the memory area is allocated. The releaser releases the memory area from the processor to which the memory area is allocated when a sum of the values of the reference counters in the memory area updated by the updater is 0.
    Type: Application
    Filed: February 15, 2011
    Publication date: April 26, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Nobuhiro Nonogaki
  • Patent number: 8108622
    Abstract: A memory management system includes a plurality of processors, a shared memory that can be accessed from the plurality of processors, cache memories provided between each processor of the plurality of processors and the shared memory and invalidation or write back of a specified region can be commanded from a program running on a processor. Programs running on each processor invalidate an input data region of a cache memory with an invalidation command immediately before execution of a program as a processing batch, and write back an output data region of a cache memory to the shared memory with a write back command immediately after execution of a program as a processing batch.
    Type: Grant
    Filed: February 15, 2008
    Date of Patent: January 31, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Nobuhiro Nonogaki, Takeshi Kodaka
  • Publication number: 20110061058
    Abstract: A task scheduling method and multi-core system according to an embodiment of the present invention comprises: in scheduling for selecting a task that is set in an execution state with a microprocessor allocated thereto out of tasks in an executable state, it is determined whether at least one of the tasks in a young generation, for which the number of times of refill performed until a point of scheduling after transitioning from the execution state to a standby state according to release of the microprocessor is smaller than a predetermined number of times, is present and, when at least one of the tasks in the young generation is present, microprocessor is allocated to the task selected from at least one of the tasks of the young generation.
    Type: Application
    Filed: April 27, 2010
    Publication date: March 10, 2011
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Nobuhiro NONOGAKI
  • Patent number: 7822591
    Abstract: A logic circuit model conversion apparatus includes a first analysis unit which analyzes a model in which a logic circuit of a register transfer level has been coded and outputs simultaneous blocks and an analysis result, a creating unit which creates a common execution frequency group that is a set of codes whose execution frequency becomes common, based on the simultaneous blocks and analysis result, a second analysis unit which analyzes the common execution frequency group and creates a formula of a general term to derive a predetermined value of each register, a third analysis unit which analyzes a mutual relationship between the common execution frequency groups and derives an execution frequency of each common execution frequency group up to a predetermined time, and a deriving unit which derives a value of each of the registers at the predetermined time from the formula of the general term and execution frequency.
    Type: Grant
    Filed: September 22, 2006
    Date of Patent: October 26, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomoshi Otsuki, Nobuhiro Nonogaki
  • Publication number: 20100241920
    Abstract: An image decoding apparatus is an image decoding apparatus that parses an input bit stream to extract decode parameters and generates a decoded image based on the decode parameters. The image decoding apparatus includes: an error position/recovery position detecting unit that detects an error position and a recovery position in the decode parameters and discards the decode parameters in the error position to the recovery position; and an interpolated-decode-parameter inserting unit that interpolates the decode parameters discarded by the error position/recovery position detecting unit.
    Type: Application
    Filed: November 6, 2009
    Publication date: September 23, 2010
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Nobuhiro Nonogaki
  • Publication number: 20100118960
    Abstract: An image decoding apparatus includes a syntax-element compressing unit that executes compression processing on syntax elements extracted in syntax analysis processing and classifies the syntax elements based on types thereof, a plurality of syntax-element expanding units that correspond to any one of classified groups of syntax elements in a one to one relation and expand the syntax elements belonging to the corresponding group to restore the original syntax elements, and a plurality of signal processing units that correspond to any one of the syntax-element expanding units in a one to one relation and apply, to the syntax elements restored by the corresponding syntax-element expanding unit, signal processing corresponding to a type thereof.
    Type: Application
    Filed: June 29, 2009
    Publication date: May 13, 2010
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Nobuhiro Nonogaki
  • Publication number: 20090254710
    Abstract: A cache memory control device according to an embodiment of the present invention comprises: a refill counter that counts a refill request, and a cache-capacity determining unit that determines cache capacity. The cache-capacity determining unit transmits a cache-capacity-decrease command signal to the cache memory when a count value is equal to or smaller than a first threshold value or is smaller than the first threshold value, and the cache-capacity determining unit transmits a cache-capacity-increase command signal to the cache memory when the count value is equal to or larger than a second threshold value, which is larger than the first threshold value, or when the count value is larger than the second threshold value.
    Type: Application
    Filed: February 17, 2009
    Publication date: October 8, 2009
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Nobuhiro NONOGAKI
  • Publication number: 20090244364
    Abstract: A moving image separating apparatus is disclosed. The apparatus is provided with a privacy image region detection unit and a moving image separating unit. The privacy image region detection unit detects privacy image region data indicating a position and a range of a privacy image region from the original moving image data. The moving image separating unit receives the original moving image data and the privacy image region data from the privacy image region detection unit. The moving image separating unit separates the original moving image data to private moving image data composed of image data corresponding to the privacy image region and to public moving image data composed of image data of a region excluding the privacy image region, on the basis of the privacy image region data.
    Type: Application
    Filed: March 26, 2009
    Publication date: October 1, 2009
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Nobuhiro Nonogaki