Patents by Inventor Nobuhiro Tanabe

Nobuhiro Tanabe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150108570
    Abstract: A transistor having a trench gate is controlled such that values settable as on current of the transistor are not discrete. A first transistor includes a plurality of first trenches, a first gate insulating film, and a first gate electrode. The first trenches are provided on a substrate, and are arranged side by side in a plan view. The first gate insulating film is provided on at least a side face of each of the first trenches, and over each of substrate regions located between the first trenches. The first gate electrode is embedded in each of the first trenches, and is provided over each of regions of the first gate insulating film located between the first trenches. At least one of the first trenches is formed as a circular trench in a plan view.
    Type: Application
    Filed: October 10, 2014
    Publication date: April 23, 2015
    Applicant: Renesas Electronics Corporation
    Inventors: Naoyoshi KAWAHARA, Nobuhiro TANABE
  • Patent number: 8097345
    Abstract: Disclosed is an excellent gas barrier laminate whose gas-barrier property has little dependency on temperature and which hardly causes fracture even when the laminate is stretched. A gas barrier film comprising a polymer (A) of an unsaturated carboxylic acid compound monovalent metal salt (a), wherein the polymer (A) contains a modified vinyl alcohol polymer (B); a gas barrier laminate comprising a base layer and the gas barrier film formed on at least one surface of the base layer; and a method for production of a gas barrier laminate comprising the steps of: coating a solution of an unsaturated carboxylic acid compound monovalent metal salt (a) having a polymerization degree less than 20 on at least one surface of a base layer, wherein the solution contains a modified vinyl alcohol polymer (B); performing the polymerization to form a layer of the polymer (A) of the unsaturated carboxylic acid compound monovalent metal salt (a) containing the modified vinyl alcohol polymer (B).
    Type: Grant
    Filed: August 30, 2006
    Date of Patent: January 17, 2012
    Assignee: Tohcello Co., Ltd.
    Inventors: Tomoyoshi Hakamata, Akira Nomoto, Osamu Nakamura, Yoshihisa Inoue, Kou Tsurugi, Nobuhiro Tanabe, Yoshihiro Yamamoto
  • Publication number: 20090269592
    Abstract: Disclosed is an excellent gas barrier laminate whose gas-barrier property has little dependency on temperature and which hardly causes fracture even when the laminate is stretched. A gas barrier film comprising a polymer (A) of an unsaturated carboxylic acid compound monovalent metal salt (a), wherein the polymer (A) contains a modified vinyl alcohol polymer (B); a gas barrier laminate comprising a base layer and the gas barrier film formed on at least one surface of the base layer; and a method for production of a gas barrier laminate comprising the steps of: coating a solution of an unsaturated carboxylic acid compound monovalent metal salt (a) having a polymerization degree less than 20 on at least one surface of a base layer, wherein the solution contains a modified vinyl alcohol polymer (B); performing the polymerizaton to form a layer of the polymer (A) of the unsaturated carboxylic acid compound monovalent metal salt (a) containing the modified vinyl alcohol polymer (B).
    Type: Application
    Filed: August 30, 2006
    Publication date: October 29, 2009
    Applicant: TOHCELLO CO., LTD.
    Inventors: Tomoyoshi Hakamata, Akira Nomoto, Osamu Nakamura, Yoshihisa Inoue, Kou Tsurugi, Nobuhiro Tanabe, Yoshihiro Yamamoto
  • Patent number: 6323510
    Abstract: A semiconductor memory device is provided, which prevents the characteristic of storage capacitors from degrading without chip-area increase of memory cells. Each of storage capacitors has a dielectric sandwiched by lower and upper electrodes. The lower electrodes are formed by a patterned, common electrically-conductive layer. The dielectrics are formed by a patterned, common ferroelectric layer formed on the common electrically-conductive layer which is entirely overlapped with the common electrically-conductive layer. The upper electrodes are regularly arranged on the common ferroelectric layer and are located outside the rows and columns of a matrix array where the windows of the common electrically-conductive layer and common ferroelectric layer are aligned. Wiring lines are formed over the upper electrodes through an interlayer insulating layer covering the storage capacitors, thereby electrically connecting the upper electrodes and select transistors.
    Type: Grant
    Filed: February 13, 1998
    Date of Patent: November 27, 2001
    Assignee: NEC Corporation
    Inventors: Nobuhiro Tanabe, Kazushi Amanuma
  • Patent number: 6004839
    Abstract: In a method of manufacturing a semiconductor device, a CMOS section composed of an N-channel MOS transistor and a P-channel MOS transistor and a memory section composed of at least a transfer gate MOS transistor is formed on a substrate. A plurality of conductive plugs is formed to penetrate a laminate insulating film to the MOS transistors. The laminate insulating film is composed of a first insulating film and a second insulating film. A capacitor section is formed on the laminate insulating film and the capacitor section is composed of an upper electrode, a dielectric film and a lower electrode. A third insulating film is formed on the laminate insulating film and the capacitor section. A wiring pattern is formed on the third insulating film to partially penetrate the second insulating film connect to the plurality of conductive plugs. A wiring pattern may be disposed in the laminate insulating film to connect at least two of the plurality of conductive plugs.
    Type: Grant
    Filed: February 20, 1997
    Date of Patent: December 21, 1999
    Assignee: NEC Corporation
    Inventors: Yoshihiro Hayashi, Nobuhiro Tanabe, Tsuneo Takeuchi, Shinobu Saito
  • Patent number: 6002608
    Abstract: In a ferroelectric memory, a malfunction in which data are reversed at the time of writing after reading out of data is prevented. Using a transistor to short-circuit two common lines which are connected to a memory element, the two common lines are short-circuited at the preparing stage for writing new data, and thereby such a malfunction which occurs reversal of data owing to an electric potential difference between common lines is prevented.
    Type: Grant
    Filed: June 15, 1998
    Date of Patent: December 14, 1999
    Assignee: NEC Corporation
    Inventor: Nobuhiro Tanabe
  • Patent number: 5391901
    Abstract: A plurality of word lines extend linearly and parallel to each other. A reference word line is positioned to divide the word lines into two groups of word lines. A plurality of bit lines are folded on the reference word line symmetrically with respect to the reference word line and spaced at intervals from each other. Each of memory elements comprises a capacitive element and a switching transistor having a source connected to the capacitive element, a drain connected to one of the bit lines, and a gate connected to one of the word lines. The memory elements are disposed in a matrix such that they are spaced across and along the word lines and paired memory elements whose switching transistors have drains connected to the same bit line are positioned symmetrically with respect to the reference word line.
    Type: Grant
    Filed: October 22, 1993
    Date of Patent: February 21, 1995
    Assignee: NEC Corporation
    Inventor: Nobuhiro Tanabe