Abstract: A fine-adjustment synthesizer includes a fractional phase-locked loop having a reference integer frequency divider, a phase comparator, a loop filter, a frequency variable oscillator, a mixer, a baud-pass filter, and a feedback path programmable fractional frequency divider. A coarse-adjustment synthesizer includes an integer-type phase-locked loop having a reference integer frequency divider, a phase comparator, a loop filter, a frequency variable oscillator, a band-pass filter, and a feedback path programmable integer frequency divider. An output of a reference signal source is input in parallel to both the fine-adjustment synthesizer and the coarse-adjustment synthesizer. An output of the frequency variable oscillator in the fine-adjustment synthesizer and an output of the frequency variable oscillator in the coarse-adjustment synthesizer are guided to the mixer and an output signal of the fine-adjustment synthesizer is guided to an output end.

Abstract: A fine-adjustment synthesizer includes a fractional phase-locked loop having a reference integer frequency divider, a phase comparator, a loop filter, a frequency variable oscillator, a mixer, a hand-pass filter, and a feedback path programmable fractional frequency divider. A coarse-adjustment synthesizer includes an integer-type phase-locked loop having a reference integer frequency divider, a phase comparator, a loop filter, a frequency variable oscillator, a band-pass filter, and a feedback path programmable integer frequency divider. An output of a reference signal source is input in parallel to both the fine-adjustment synthesizer and the coarse-adjustment synthesizer. An output of the frequency variable oscillator in the fine-adjustment synthesizer and an output of the frequency variable oscillator in the coarse-adjustment synthesizer are guided to the mixer and an output signal of the fine-adjustment synthesizer is guided to an output end.

Abstract: There is provided an IC package provided with one or more bare chips mounted on a chip carrier, a plurality of first bumps each for connecting a chip electrode to a conductive pad disposed on an upper surface of the chip carrier, a plurality of second bumps each connected to a conductive pad disposed on a bottom surface of the chip carrier, and a plurality of vias for connecting between conductive pads disposed on the upper and bottom surfaces of the chip carrier. A differential pair of lines are exposed on the upper surface of the chip carrier. High-frequency signals to be processed by the one or more bare chips are transmitted by way of the differential pair of lines, and other signals are transmitted by way of the plurality of second bumps.

Abstract: There is provided an IC package provided with one or more bare chips mounted on a chip carrier, a plurality of first bumps each for connecting a chip electrode to a conductive pad disposed on an upper surface of the chip carrier, a plurality of second bumps each connected to a conductive pad disposed on a bottom surface of the chip carrier, and a plurality of vias for connecting between conductive pads disposed on the upper and bottom surfaces of the chip carrier. A differential pair of lines are exposed on the upper surface of the chip carrier. High-frequency signals to be processed by the one or more bare chips are transmitted by way of the differential pair of lines, and other signals are transmitted by way of the plurality of second bumps.

Abstract: There is provided an IC package provided with one or more bare chips mounted on a chip carrier, a plurality of first bumps each for connecting a chip electrode to a conductive pad disposed on an upper surface of the chip carrier, a plurality of second bumps each connected to a conductive pad disposed on a bottom surface of the chip carrier, and a plurality of vias for connecting between conductive pads disposed on the upper and bottom surfaces of the chip carrier. A differential pair of lines are exposed on the upper surface of the chip carrier. High-frequency signals to be processed by the one or more bare chips are transmitted by way of the differential pair of lines, and other signals are transmitted by way of the plurality of second bumps.

Abstract: There is provided an IC package provided with one or more bare chips mounted on a chip carrier, a plurality of first bumps each for connecting a chip electrode to a conductive pad disposed on an upper surface of the chip carrier, a plurality of second bumps each connected to a conductive pad disposed on a bottom surface of the chip carrier, and a plurality of vias for connecting between conductive pads disposed on the upper and bottom surfaces of the chip carrier. A differential pair of lines are exposed on the upper surface of the chip carrier. High-frequency signals to be processed by the one or more bare chips are transmitted by way of the differential pair of lines, and other signals are transmitted by way of the plurality of second bumps.