Abstract: A DML driver (10) includes a PMOS transistor (M1p) having a gate connected to a bias voltage (V2), a source connected to a power supply voltage (V1), and a drain connected to the anode of an LD (1), an NMOS transistor (M1n) having a source connected to ground, an inductor (L1) having one end to which a modulated signal (Vin) is input, and the other end connected to the gate of the NMOS transistor (M1n), and a resistor (Rin) having one end connected to a bias voltage (V4), and the other end connected to one end of the inductor (L1).

Abstract: An embodiment is a directly modulated laser (DML) driver, including a PMOS transistor having a source connected to a first power supply terminal and a drain connected to an anode of a laser diode, an NMOS transistor having a gate configured to be connected to an modulated input signal, and a source connected to a second power supply terminal, a resistor having one end connected to a first bias terminal, and the other end connected to the gate of the PMOS transistor, a first decoupling capacitor having one end connected to the first power supply terminal, and the other end connected to the second power supply terminal, and a plurality of decoupling capacitors each having one end connected to a respective bias terminal, and the other end connected to the first power supply terminal.

Abstract: The transmission interface includes a plurality of transmitters, wherein the transmitters are provided with: a power supply terminal shared by the plurality of transmitters, configured to receive a ground voltage; a bias terminal configured to receive a bias voltage; signal terminals configured to receive a signal voltage; a power supply fluctuation inverting bias unit to which a ground voltage and a bias voltage are applied, and which outputs the ground voltage making its fluctuation 180 degrees out of phase; a modulation unit to which the output of the power supply fluctuation inverting bias unit and a signal voltage are applied, and which outputs the opposite phase ground voltage making its fluctuation in phase; and a laser diode to which the ground voltage and the output of the modulation unit are applied.

Abstract: In a phase sync circuit (40) which extracts a clock signal CK from a data signal D in a random NRZ format, particularly in a phase sync circuit (40) of a dual loop configuration including both a phase comparison circuit (81) and a frequency comparison circuit (10), a phase sync circuit (40) capable of achieving both broadening of the capture range and extraction of a high-quality clock signal without requiring any reference clock signal is provided. A clock signal Ca, another clock signal Cb having a phase delayed by an approximately ¼ period from the clock signal Ca and the data signal D are input to the frequency comparison circuit (10) to output a logical value according to the high-low relationship between the frequency of the clock signal and the bit rate of the data signal D.

Abstract: In a phase sync circuit (40) which extracts a clock signal CK from a data signal D in a random NRZ format, particularly in a phase sync circuit (40) of a dual loop configuration including both a phase comparison circuit (81) and a frequency comparison circuit (10), a phase sync circuit (40) capable of achieving both broadening of the capture range and extraction of a high-quality clock signal without requiring any reference clock signal is provided. A clock signal Ca, another clock signal Cb having a phase delayed by an approximately ¼ period from the clock signal Ca and the data signal D are input to the frequency comparison circuit (10) to output a logical value according to the high-low relationship between the frequency of the clock signal and the bit rate of the data signal D.