Abstract: A read process is performed on an ith designated block storing an ith divided data string. If the ith divided data string is not normally read, the read process is sequentially executed on ith ordinary blocks each storing the ith divided data string, where the ith ordinary blocks are included in ordinary block groups, respectively. When the ith divided data string is normally read, it is determined whether or not reading p divided data strings has been completed. If it is determined that the reading the p divided data strings has not been completed, the read process is performed on an (i+1)th designated block storing an (i+1)th divided data string following the ith divided data string.

Abstract: In the cache circuit, an instruction cache hit counter counts the number of cache hits, and an instruction memory access counter counts the number of times of instruction access. An instruction cache hit rate computation/entry disabling control circuit computes the ratio of the cache hit count to the instruction access count (cache hit rate). If the cache hit rate exceeds an instruction cache entry disabling threshold, an instruction cache control circuit disables contents of instruction cache memory.

Abstract: An interrupt control circuit has a condition storage circuit for storing and outputting a reference time and an error detection circuit for outputting a signal indicating error detection when an interrupt request is not generated within a period from a predetermined time till the reference time elapses.

Abstract: A debugging system which can efficiently obtain debugging information and which has excellent debugging efficiency is a debugging system which stops execution of a program executed in a program executing apparatus, at a break point, and assists debugging of the program, and which includes: a dump control unit configured to dump information indicating an operating state of the program executing apparatus, at plural points in time prior to the stopping of the execution of the program; and a dump information accumulating unit configured to accumulate the information indicating the operating state of the program executing apparatus dumped by said dump control unit.

Abstract: An interrupt control circuit has a condition storage circuit for storing and outputting a reference time and an error detection circuit for outputting a signal indicating error detection when an interrupt request is not generated within a period from a predetermined time till the reference time elapses.

Abstract: In the cache circuit, an instruction cache hit counter counts the number of cache hits, and an instruction memory access counter counts the number of times of instruction access. An instruction cache hit rate computation/entry disabling control circuit computes the ratio of the cache hit count to the instruction access count (cache hit rate). If the cache hit rate exceeds an instruction cache entry disabling threshold, an instruction cache control circuit disables contents of instruction cache memory.