Abstract: A suction-holding apparatus includes a suction plate made of an air-permeable material, a holding member formed with a through-hole in which the suction plate is placed, and a base to which the holding member is attached. The suction plate includes a jutting-out portion so that the outer edge of the rear face is disposed outwardly from the outer edge of the front face. The through-hole includes a first edge and a second edge spaced apart from each other in the thickness direction. The first edge is adjacent to the base. The holding member includes an eaved portion so that the second edge of the through-hole is disposed inwardly from the outer edge of the rear face.

Abstract: A suction-holding apparatus includes a suction plate made of an air-permeable material, a holding member formed with a through-hole in which the suction plate is placed, and a base to which the holding member is attached. The suction plate includes a jutting-out portion so that the outer edge of the rear face is disposed outwardly from the outer edge of the front face. The through-hole includes a first edge and a second edge spaced apart from each other in the thickness direction. The first edge is adjacent to the base. The holding member includes an eaved portion so that the second edge of the through-hole is disposed inwardly from the outer edge of the rear face.

Abstract: A semiconductor chip including a bump projecting from a surface protective film thereof and a surface interconnection having a smaller height than the bump. The surface interconnection may project from the surface protective film or may be flush with the surface protective film. The surface interconnection may be connected to the bump. The bump may include a peripheral bump configured as surrounding a device formation region of the chip. The peripheral bump may be connected to the ground or a power source.

Abstract: A semiconductor chip including a bump projecting from a surface protective film thereof and a surface interconnection having a smaller height than the bump. The surface interconnection may project from the surface protective film or may be flush with the surface protective film. The surface interconnection may be connected to the bump. The bump may include a peripheral bump configured as surrounding a device formation region of the chip. The peripheral bump may be connected to the ground or a power source.

Abstract: A semiconductor chip having a functional bump provided on a surface of a semiconductor substrate thereof for electrical connection between an internal circuit thereof and a solid device, and a dummy bump not serving for the electrical connection between the internal circuit and the solid device. The dummy bump may be a stress relieving bump for relieving stresses exerted thereon. The dummy bump may be connected to a low impedance portion. The functional bump and the dummy bump may be provided on a surface protective film. In this case, the dummy bump is provided on a recess formed in the surface protective film.

Abstract: A semiconductor device includes an insulating film. On this insulating film are formed an interconnection trench communicating with a semiconductor element and a pad trench communicating with the interconnection trench. In the pad trench, a protrusion is formed by leaving one part of the insulating film. A conductive film is formed over the insulating film including the interconnection and pad trenches. Thereafter, the conductive film is removed by a CMP process. At this time, the protrusion serves to prevent the conductive film in the pad trench from being over-polished.

Abstract: A semiconductor device includes an insulating film. On this insulating film, formed are an interconnection trench communicating with a semiconductor element and a pad trench communicating with the interconnection trench. In the pad trench, a protrusion is formed by leaving one part of the insulating film. A conductive film is formed over the insulating film including the interconnection and pad trenches. Thereafter, the conductive film is removed by a CMP process. At this time, the protrusion serves to prevent the conductive film in the pad trench from being over-polished.

Abstract: A semiconductor device having a metal layer at the peripheral area surrounding an element forming area formed on a semiconductor substrate. This metal layer may be connected to the grounding potential or the power potential. The peripheral area is a scribing line area for example. The metal layer may be formed simultaneously with the formation of a bump within the element forming area.

Abstract: A semiconductor device includes an insulating film. On this insulating film, are formed an interconnection trench communicating with a semiconductor element and a pad trench communicating with the interconnection trench. In the pad trench, a protrusion is formed by leaving one part of the insulating film. A conductive film is formed over the insulating film including the interconnection and pad trenches. Thereafter, the conductive film is removed by a CMP process. At this time, the protrusion serves to prevent the conductive film in the pad trench from being over-polished.

Abstract: A semiconductor chip (3) to be positioned with a front face thereof downward for formation of a chip-on-chip structure has electrode marks (35) provided on a back face (34) thereof. The electrode marks (35) are respectively provided in association with a plurality of electrodes (33) provided on the front face (31) of the semiconductor chip in the same arrangement as the arrangement of the electrodes (33). The arrangement of the electrode marks (35) represents the arrangement of the electrodes (33) on the front face (31) when viewed from the side of the back face (34) of the semiconductor chip 3. Therefore, the semiconductor chip (3) can easily be positioned with the front face downward on the basis of the electrode marks (35).

Abstract: A semiconductor chip having a functional bump provided on a surface of a semiconductor substrate thereof for electrical connection between an internal circuit thereof and a solid device, and a dummy bump not serving for the electrical connection between the internal circuit and the solid device. The dummy bump may be a stress relieving bump for relieving stresses exerted thereon. The dummy bump may be connected to a low impedance portion. The functional bump and the dummy bump may be provided on a surface protective film. In this case, the dummy bump is provided on a recess formed in the surface protective film.

Abstract: A semiconductor chip including a bump projecting from a surface protective film thereof and a surface interconnection having a smaller height than the bump. The surface interconnection may project from the surface protective film or may be flush with the surface protective film. The surface interconnection may be connected to the bump. The bump may include a peripheral bump configured as surrounding a device formation region of the chip. The peripheral bump may be connected to the ground or a power source.

Abstract: A semiconductor chip having a functional bump provided on a surface of a semiconductor substrate thereof for electrical connection between an internal circuit thereof and a solid device, and a dummy bump not serving for the electrical connection between the internal circuit and the solid device. The dummy bump may be a stress relieving bump for relieving stresses exerted thereon. The dummy bump may be connected to a low impedance portion. The functional bump and the dummy bump may be provided on a surface protective film. In this case, the dummy bump is provided on a recess formed in the surface protective film.

Abstract: A semiconductor chip including a bump projecting from a surface protective film thereof and a surface interconnection having a smaller height than the bump. The surface interconnection may project from the surface protective film or may be flush with the surface protective film. The surface interconnection may be connected to the bump. The bump may include a peripheral bump configured as surrounding a device formation region of the chip. The peripheral bump may be connected to the ground or a power source.

Abstract: A semiconductor chip (3) to be positioned with a front face thereof downward for formation of a chip-on-chip structure has electrode marks (35) provided on a back face (34) thereof. The electrode marks (35) are respectively provided in association with a plurality of electrodes (33) provided on the front face (31) of the semiconductor chip in the same arrangement as the arrangement of the electrodes (33). The arrangement of the electrode marks (35) represents the arrangement of the electrodes (33) on the front face (31) when viewed from the side of the back face (34) of the semiconductor chip 3. Therefore, the semiconductor chip (3) can easily be positioned with the front face downward on the basis of the electrode marks (35).

Abstract: A semiconductor chip (3) to be positioned with a front face thereof downward for formation of a chip-on-chip structure has electrode marks (35) provided on a back face (34) thereof. The electrode marks (35) are respectively provided in association with a plurality of electrodes (33) provided on the front face (31) of the semiconductor chip in the same arrangement as the arrangement of the electrodes (33). The arrangement of the electrode marks (35) represents the arrangement of the electrodes (33) on the front face (31) when viewed from the side of the back face (34) of the semiconductor chip 3. Therefore, the semiconductor chip (3) can easily be positioned with the front face downward on the basis of the electrode marks (35).

Abstract: In the case of providing a contact hole (2a) in an insulting film (2) on the substrate (1), and forming a wiring on the insulting film to be connected to an exposed portion by the contact hole, a tin film (4) is formed on a location where the wiring is formed, and a paradium film (5) is formed on a location where the wiring is formed by immersing a portion where the tin film is provided in a solution containing a paradium ion (Pd2+). Then, the paradium film is used as a reaction start layer to form a copper film (6) by the electroless plating method. Furthermore, a second copper film may be formed by the electroplating by using the copper film as the feeder layer. By doing so, there is provided a semiconductor device wherein the diffusion of elements of the reaction start layer (the seed layer) into the film is prevented, a copper film having a small specific resistance and excellent conductivity formed with good reliability, and a higher integration can be provided with further fine wiring.

Abstract: A semiconductor device having a metal layer at the peripheral area surrounding an element forming area formed on a semiconductor substrate. This metal layer may be connected to the grounding potential or the power potential. The peripheral area is a scribing line area for example. The metal layer may be formed simultaneously with the formation of a bump within the element forming area.

Abstract: A semiconductor device having a metal layer at the peripheral area surrounding an element forming area formed on a semiconductor substrate. This metal layer may be connected to the grounding potential or the power potential. The peripheral area is a scribing line area for example. The metal layer may be formed simultaneously with the formation of a bump within the element forming area.

Abstract: A semiconductor device having a solid device, and a semiconductor chip bonded to the solid device with a back face thereof being opposed to a front face of the solid device. The semiconductor chip has a back electrode provided on the back face thereof and electrically connected to an electrode provided on a front face thereof through a through-hole. The solid device may be a wiring board or another semiconductor chip. Further another semiconductor chip may be stacked and bonded onto the front face of the semiconductor chip.