Patents by Inventor Nobuhisa Nakashima
Nobuhisa Nakashima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11944427Abstract: The learning system includes a data generation unit configured to generate learning data based on rehabilitation data and a learning unit configured to perform machine learning using the learning data. A sensor is provided to detect a plurality of motion amounts in a walking motion of a trainee, and it is evaluated that, when one of the motion amounts matches one of abnormal walking criteria, that the walking motion is an abnormal walking pattern that meets the matched abnormal walking criterion. The data generation unit generates each of the pieces of rehabilitation data before and after a change in the results of evaluation of the abnormal walking pattern as learning data. The learning unit sequentially inputs each of the pieces of rehabilitation data as one data set, thereby performing machine learning.Type: GrantFiled: May 28, 2020Date of Patent: April 2, 2024Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Nobuhisa Otsuki, Issei Nakashima, Manabu Yamamoto, Hodaka Kito
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Patent number: 11937918Abstract: The learning apparatus includes a data generation unit configured to generate learning data based on rehabilitation data and a learning unit configured to perform machine learning using the learning data. A sensor is provided to detect a plurality of motion amounts in a walking motion of a trainee, and it is evaluated that, when one of the motion amounts matches one of abnormal walking criteria, that the walking motion is an abnormal walking pattern that meets the matched abnormal walking criterion. The data generation unit generates each of the pieces of rehabilitation data before and after a change in the results of evaluation of the abnormal walking pattern as learning data. The learning unit sequentially inputs each of the pieces of rehabilitation data as one data set, thereby performing machine learning.Type: GrantFiled: May 28, 2020Date of Patent: March 26, 2024Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Nobuhisa Otsuki, Issei Nakashima, Manabu Yamamoto, Hodaka Kito
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Patent number: 11929173Abstract: The server is a learning apparatus including a data acquisition unit and a learning unit. The data acquisition unit acquires profile data and a selected assistance level as learning data. The profile data indicates a profile related to a trainee before executing rehabilitation regarding rehabilitation executed using a walking training apparatus as a rehabilitation support system. The selected assistance level is an assistance level selected at the time of executing the rehabilitation. The learning unit learns to determine a recommended assistance level recommended to be selected when the trainee uses the rehabilitation support system based on the learning data. Further, the learning unit generates a trained model that receives the profile data and outputs the recommended assistance level based on the learning.Type: GrantFiled: June 30, 2020Date of Patent: March 12, 2024Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Nobuhisa Otsuki, Ai Kurokawa, Issei Nakashima, Manabu Yamamoto, Taiga Matsumoto, Hiroaki Daba
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Patent number: 7242036Abstract: A semiconductor element includes a first semiconductor layer of a first conductivity type including a non-deposition region and a deposition region. The first semiconductor layer has a first upper surface on the non-deposition region. The semiconductor element also includes a second semiconductor layer of a second conductivity type on the deposition region of the first semiconductor layer. The second semiconductor layer has a second upper surface. The semiconductor element includes first and second electrode layers on the first and second semiconductor layers, respectively, which define an inclined surface for continuous connection therebetween. The semiconductor element includes an insulating layer on the inclined surface, spaced from at least either one of the first and second electrode layers. At least either one of the first and second semiconductor layers includes a recessed portion between the respective one of the first and second electrode layers and the insulating layer.Type: GrantFiled: December 29, 2006Date of Patent: July 10, 2007Assignee: Mitsubishi Electric CorporationInventor: Nobuhisa Nakashima
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Patent number: 6864515Abstract: Each of outermost segments (OMSG) and innermost segments (IMSG) is utilized as a dummy segment. A top surface of a protruding portion (OMPP, IMPP) of each of the outermost segments (OMSG) and the innermost segments (IMSG) is covered with an insulating layer (1S+1P), and a clearance (CL) is provided between a top surface of the insulating layer (1S+1P) and a bottom surface (2BS) of a cathode strain relief plate. Each of all the other segments (SG) than the outermost and innermost segments has a protruding portion PP on which a cathode electrode (1K-AL) is formed. A thickness (T1) of the cathode electrode (1K-AL) is determined so as to allow a top surface of the cathode electrode (1K-AL) to be in contact with the bottom surface (2BS) of the cathode strain relief plate.Type: GrantFiled: July 14, 2003Date of Patent: March 8, 2005Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Nobuhisa Nakashima, Teruya Fukaura, Kenji Oota
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Publication number: 20040164316Abstract: Each of outermost segments (OMSG) and innermost segments (IMSG) is utilized as a dummy segment. A top surface of a protruding portion (OMPP, IMPP) of each of the outermost segments (OMSG) and the innermost segments (IMSG) is covered with an insulating layer (1S+1P), and a clearance (CL) is provided between a top surface of the insulating layer (1S+1P) and a bottom surface (2BS) of a cathode strain relief plate. Each of all the other segments (SG) than the outermost and innermost segments has a protruding portion PP on which a cathode electrode (1K−AL) is formed. A thickness (T1) of the cathode electrode (1K−AL) is determined so as to allow a top surface of the cathode electrode (1K−AL) to be in contact with the bottom surface (2BS) of the cathode strain relief plate.Type: ApplicationFiled: July 14, 2003Publication date: August 26, 2004Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Nobuhisa Nakashima, Teruya Fukaura, Kenji Oota
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Patent number: 5633536Abstract: Provided is a press contact type semiconductor device which improves the shape of an insulator formed along an outer peripheral edge and a major surface of a semiconductor substrate, simplifies alignment of an anode heat compensator and a cathode heat compensator, causes no biting, causes no separation in molding, and has excellent heat dissipation. In the press contact type semiconductor device, the inner periphery of a ring-shaped insulator (22) which is formed along an edge of the overall periphery and a major surface of a semiconductor substrate (6) provided with a P-N junction in its interior comprises a tapered portion (22a) along the inner peripheral direction and a vertical portion (22b) forming a perpendicular inner peripheral diameter which is continuous to this tapered portion (22a).Type: GrantFiled: December 5, 1995Date of Patent: May 27, 1997Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Nobuhisa Nakashima, Yuzuru Konishi, Tokumitsu Sakamoto
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Patent number: 5519231Abstract: In order to obtain a pressure-connection type semiconductor device while preventing misregistration of a semiconductor base substrate and a thermal compensator with no penetration of an insulating/holding material and a method suitable for fabricating this device, concentric first and second steps (31c, 31a) are provided on an upper major surface of a first thermal compensator (31) from its outer periphery toward the center. A corner groove (3b) is provided along the overall periphery of an inner comer of the first step (31c), in the form of a ring. Since no insulating/holding material is provided in a contact surface between the semiconductor the substrate and the thermal compensator, the semiconductor base substrate and the thermal compensator are maintained in excellent electrical contact while no local stress is applied to the semiconductor substrate when the same is brought into pressure contact with the thermal compensator.Type: GrantFiled: November 15, 1994Date of Patent: May 21, 1996Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Nobuhisa Nakashima, Tokumitsu Sakamoto, Yuzuru Konishi
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Patent number: 5100809Abstract: A silicon substrate (20) having a pnpn structure is soldered to a metal plate (10). A silicon oxide film (16) is naturally formed on the side surface of the silicon substrate during a process of removing defective part of the side surface, and a metal component penetrates into the silicon oxide film. The silicon substrate is dipped into an etchant to etch the silicon oxide film, so that a leak current through the metal component is effectively prevented.Type: GrantFiled: February 5, 1991Date of Patent: March 31, 1992Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Nobuhisa Nakashima, Tokumitsu Sakamoto