Patents by Inventor Nobuhisa Takakusaki

Nobuhisa Takakusaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7854062
    Abstract: A method for manufacturing a circuit device, which is suitable for connecting a plurality of laminated wiring layers to each other through an insulating layer, is provided. In a method for manufacturing a hybrid integrated circuit device of the present invention, a first wring layer is formed by laminating a first conductive film on a first insulating layer, and patterning the first conductive film. In the first wiring layer, a first connection part which is protruded in a thickness direction is formed. Moreover, the first wiring layer including the first connection part is covered with a second insulating layer. The second insulating layer is formed of a first resin film and a second resin film. The second resin film contains fewer inorganic fillers than the first resin film. Thus, there is an advantage that a through-hole can be easily formed.
    Type: Grant
    Filed: January 12, 2009
    Date of Patent: December 21, 2010
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Ryosuke Usui, Hideki Mizuhara, Yusuke Igarashi, Nobuhisa Takakusaki, Takeshi Nakamura
  • Patent number: 7565738
    Abstract: A method for manufacturing a circuit device, which is suitable for connecting a plurality of laminated wiring layers to each other through an insulating layer, is provided. In a method for manufacturing a hybrid integrated circuit device of the present invention, a first wring layer is formed by laminating a first conductive film on a first insulating layer, and patterning the first conductive film. In the first wiring layer, a first connection part which is protruded in a thickness direction is formed. Moreover, the first wiring layer including the first connection part is covered with a second insulating layer. The second insulating layer is formed of a first resin film and a second resin film. The second resin film contains fewer inorganic fillers than the first resin film. Thus, there is an advantage that a through-hole can be easily formed.
    Type: Grant
    Filed: May 25, 2005
    Date of Patent: July 28, 2009
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Ryosuke Usui, Hideki Mizuhara, Yusuke Igarashi, Nobuhisa Takakusaki, Hayato Abe
  • Publication number: 20090119915
    Abstract: A method for manufacturing a circuit device, which is suitable for connecting a plurality of laminated wiring layers to each other through an insulating layer, is provided. In a method for manufacturing a hybrid integrated circuit device of the present invention, a first wring layer is formed by laminating a first conductive film on a first insulating layer, and patterning the first conductive film. In the first wiring layer, a first connection part which is protruded in a thickness direction is formed. Moreover, the first wiring layer including the first connection part is covered with a second insulating layer. The second insulating layer is formed of a first resin film and a second resin film. The second resin film contains fewer inorganic fillers than the first resin film. Thus, there is an advantage that a through-hole can be easily formed.
    Type: Application
    Filed: January 12, 2009
    Publication date: May 14, 2009
    Applicant: Sanyo Electric Co., Ltd.
    Inventors: Ryosuke Usui, Hideki Mizuhara, Yusuke Igarashi, Nobuhisa Takakusaki, Hayato Aba, Takeshi Nakamura
  • Patent number: 7439614
    Abstract: In a manufacturing method of a hybrid integrated circuit device 10 according to the present invention, a first dummy pattern D1 is provided on a first wiring layer 18A. Furthermore, a second dummy pattern D2 is provided on a second wiring layer 18B. The first dummy pattern D1 and the second dummy pattern D2 are connected through a connection part 25 which penetrates an insulation layer 17. Hence, heat dissipation through a dummy pattern can be actively performed. In addition, even in the cases where a multi-layered wiring is formed, it is possible to provide a circuit device which can secure a heat dissipation property.
    Type: Grant
    Filed: May 26, 2005
    Date of Patent: October 21, 2008
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Yasunori Inoue, Ryosuke Usul, Yasuhiro Kohara, Nobuhisa Takakusaki, Takeshi Nakamura
  • Publication number: 20070226996
    Abstract: An object of the present invention is to provide a method of manufacturing a hybrid integrated circuit device, in which multiple circuit boards are manufactured from one large metal board by dicing. The hybrid integrated circuit device of the present invention includes a circuit board with a surface provided with an insulating layer, and conductive patterns provided on the insulating layer. Circuit elements are electrically connected to the conductive patterns. Further, each side surface of the circuit board includes a first inclined portion extending obliquely downward from a peripheral portion of the surface of the circuit board, and a second inclined portion extending obliquely upward from a back surface of the circuit board and formed to be larger than the first inclined portion.
    Type: Application
    Filed: May 25, 2007
    Publication date: October 4, 2007
    Applicant: SANYO ELECTRIC CO., LTD.
    Inventors: Masahiko MIZUTANI, Mitsuru NOGUCHI, Nobuhisa TAKAKUSAKI
  • Patent number: 7232957
    Abstract: An object of the present invention is to provide a method of manufacturing a hybrid integrated circuit device, in which multiple circuit boards are manufactured from one large metal board by dicing. The hybrid integrated circuit device of the present invention includes a circuit board with a surface provided with an insulating layer, and conductive patterns provided on the insulating layer. Circuit elements are electrically connected to the conductive patterns. Further, each side surface of the circuit board includes a first inclined portion extending obliquely downward from a peripheral portion of the surface of the circuit board, and a second inclined portion extending obliquely upward from a back surface of the circuit board and formed to be larger than the first inclined portion.
    Type: Grant
    Filed: September 15, 2004
    Date of Patent: June 19, 2007
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Masahiko Mizutani, Mitsuru Noguchi, Nobuhisa Takakusaki
  • Patent number: 7199468
    Abstract: In order to prevent short-circuiting when a chip component is brazed to pads of a conductive wiring layer, a hybrid semiconductor circuit includes the chip component with terminal electrodes formed at both ends, a first conductive wiring layer on which the pads are provided such that they correspond to the terminal electrodes, and an overcoat resin that covers the first conductive wiring layer excluding the pads. The terminal electrodes of the chip component are adhered to the pads by a conductive adhesive and an insulating adhesive is provided between the pads.
    Type: Grant
    Filed: March 29, 2004
    Date of Patent: April 3, 2007
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Toshimichi Naruse, Nobuhisa Takakusaki, Hajime Kobayashi
  • Patent number: 6972477
    Abstract: To make thin a circuit device 10 in which are incorporated a plurality of types of circuit elements 12 that differ in thickness, first conductive patterns, onto which comparatively thin circuit elements 12A are mounted, are formed thickly, and second conductive patterns 11B, onto which comparatively thick second circuit elements 12B are mounted, are formed thinly. Also, fine wiring parts may be formed using the thinly formed second conductive patterns 12B. Thus even in the case where thick circuit elements are incorporated, by affixing such circuit elements onto the thinly formed second conductive patterns 11B, the total thickness can be made thin. Thinning of circuit device 10 as a whole can thus be accomplished.
    Type: Grant
    Filed: December 11, 2003
    Date of Patent: December 6, 2005
    Assignees: Sanyo Electric Co., Ltd., Kanto Sanyo Semiconductors Co., Ltd.
    Inventors: Yusuke Igarashi, Nobuhisa Takakusaki, Jun Sakano, Noriaki Sakamoto
  • Publication number: 20050263905
    Abstract: A method for manufacturing a circuit device, which is suitable for connecting a plurality of laminated wiring layers to each other through an insulating layer, is provided. In a method for manufacturing a hybrid integrated circuit device of the present invention, a first wring layer is formed by laminating a first conductive film on a first insulating layer, and patterning the first conductive film. In the first wiring layer, a first connection part which is protruded in a thickness direction is formed. Moreover, the first wiring layer including the first connection part is covered with a second insulating layer. The second insulating layer is formed of a first resin film and a second resin film. The second resin film contains fewer inorganic fillers than the first resin film. Thus, there is an advantage that a through-hole can be easily formed.
    Type: Application
    Filed: May 25, 2005
    Publication date: December 1, 2005
    Inventors: Ryosuke Usul, Hideki Mizuhara, Yusuke Igarashi, Nobuhisa Takakusaki, Hayato Abe, Takeshi Nakamura
  • Patent number: 6946724
    Abstract: A circuit device 10 comprises conductive patterns 11, separated by separation grooves 41, circuit elements 12, affixed onto conductive patterns 11, and an insulating resin 13, covering circuit elements 12 and conductive patterns 11 and filling separation grooves 41 while exposing the rear surfaces of conductive patterns 11. Constricted parts 19 are formed at side surfaces of separation grooves 41. At constricted parts 19, the width of separation grooves 41 is made narrower than at other locations. Thus by making insulating resin 13 adhere closely to constricted parts 19, the adhesion of insulating resin 13 with conductive patterns 11 is improved.
    Type: Grant
    Filed: December 11, 2003
    Date of Patent: September 20, 2005
    Assignees: Sanyo Electric Co., Ltd., Kanto Sanyo Semiconductors Co., Ltd.
    Inventors: Yusuke Igarashi, Nobuhisa Takakusaki, Jun Sakano, Noriaki Sakamoto
  • Publication number: 20050067186
    Abstract: An object of the present invention is to provide a method of manufacturing a hybrid integrated circuit device, in which multiple circuit boards are manufactured from one large metal board by dicing. The hybrid integrated circuit device of the present invention includes a circuit board with a surface provided with an insulating layer, and conductive patterns provided on the insulating layer. Circuit elements are electrically connected to the conductive patterns. Further, each side surface of the circuit board includes a first inclined portion extending obliquely downward from a peripheral portion of the surface of the circuit board, and a second inclined portion extending obliquely upward from a back surface of the circuit board and formed to be larger than the first inclined portion.
    Type: Application
    Filed: September 15, 2004
    Publication date: March 31, 2005
    Applicant: Sanyo Electric Co., Ltd.
    Inventors: Masahiko Mizutani, Mitsuru Noguchi, Nobuhisa Takakusaki
  • Publication number: 20040262644
    Abstract: In order to prevent, when a chip component is brazed to pads of a conductive wiring layer, short-circuiting by a fused brazing material from short-circuiting between the pads, a hybrid semiconductor circuit comprises a chip component 43 with terminal electrodes 46 formed at both ends thereof, a first conductive wiring layer 37 on which a plurality of the pads 38 are provided to correspond to the terminal electrodes 46, and an overcoat resin 39 for covering the first conductive wiring layer 37 excluding the pads 38, and the terminal electrodes 46 of the chip component 43 is adhered to the pads 38 by a conductive adhesive 57, and an insulating adhesive 58 is provided between the pads 38.
    Type: Application
    Filed: March 29, 2004
    Publication date: December 30, 2004
    Inventors: Toshimichi Naruse, Nobuhisa Takakusaki, Hajime Kobayashi
  • Publication number: 20040169271
    Abstract: A circuit device 10 comprises conductive patterns 11, separated by separation grooves 41, circuit elements 12, affixed onto conductive patterns 11, and an insulating resin 13, covering circuit elements 12 and conductive patterns 11 and filling separation grooves 41 while exposing the rear surfaces of conductive patterns 11. Constricted parts 19 are formed at side surfaces of separation grooves 41. At constricted parts 19, the width of separation grooves 41 is made narrower than at other locations. Thus by making insulating resin 13 adhere closely to constricted parts 19, the adhesion of insulating resin 13 with conductive patterns 11 is improved.
    Type: Application
    Filed: December 11, 2003
    Publication date: September 2, 2004
    Inventors: Yusuke Igarashi, Nobuhisa Takakusaki, Jun Sakano, Noriaki Sakamoto
  • Publication number: 20040159913
    Abstract: To make thin a circuit device 10 in which are incorporated a plurality of types of circuit elements 12 that differ in thickness, first conductive patterns, onto which comparatively thin circuit elements 12A are mounted, are formed thickly, and second conductive patterns 11B, onto which comparatively thick second circuit elements 12B are mounted, are formed thinly. Also, fine wiring parts may be formed using the thinly formed second conductive patterns 12B. Thus even in the case where thick circuit elements are incorporated, by affixing such circuit elements onto the thinly formed second conductive patterns 11B, the total thickness can be made thin. Thinning of circuit device 10 as a whole can thus be accomplished.
    Type: Application
    Filed: December 11, 2003
    Publication date: August 19, 2004
    Inventors: Yusuke Igarashi, Nobuhisa Takakusaki, Jun Sakano, Noriaki Sakamoto