Abstract: An apparatus for inspecting a semiconductor device according to an embodiment includes an X-ray irradiation unit configured to make monochromatic X-rays obliquely incident on the semiconductor device, which is an object at a predetermined angle of incidence, a detection unit configured to detect observed X-rays observed from the object using a plurality of two-dimensionally disposed photodetection elements, an analysis apparatus configured to generate X-ray diffraction images obtained by photoelectrically converting the observed X-rays, and a control unit configured to change an angle of incidence and a detection angle of the X-rays, in which the analysis apparatus acquires an X-ray diffraction image every time the angle of incidence is changed, extracts a peak X-ray diffraction image, X-ray intensity of which becomes maximum for each of pixels and compares the peak X-ray diffraction image among the pixels to thereby estimate a stress distribution of the object.

Abstract: An apparatus for inspecting a semiconductor device according to an embodiment includes an X-ray irradiation unit configured to make monochromatic X-rays obliquely incident on the semiconductor device, which is an object at a predetermined angle of incidence, a detection unit configured to detect observed X-rays observed from the object using a plurality of two-dimensionally disposed photodetection elements, an analysis apparatus configured to generate X-ray diffraction images obtained by photoelectrically converting the observed X-rays, and a control unit configured to change an angle of incidence and a detection angle of the X-rays, in which the analysis apparatus acquires an X-ray diffraction image every time the angle of incidence is changed, extracts a peak X-ray diffraction image, X-ray intensity of which becomes maximum for each of pixels and compares the peak X-ray diffraction image among the pixels to thereby estimate a stress distribution of the object.

Abstract: A semiconductor wafer includes a surface having at least one recess including an inner wall surface. The inner wall surface is exposed.

Abstract: According to one embodiment, a semiconductor memory device includes a stacked body in which a plurality of insulating layers and a plurality of conductive layers are alternately stacked above a substrate, a pillar that penetrates the stacked body while extending in a stacking direction of the stacked body, and a semiconductor layer, a first insulating layer, a charge accumulation layer, and a second insulating layer, which are stacked on a side surface of the pillar in order from the pillar, wherein the semiconductor layer has an average grain size that is larger on a side nearer to the pillar and is smaller on a side nearer to the first insulating layer.

Abstract: A semiconductor storage device according to an embodiment includes a plurality of memory cells, a first film, and a second film. The memory cells are placed at intervals in a first direction on a semiconductor substrate. The first film is placed continuously in the first direction above the memory cells so as to cover all of the memory cells and including mainly metal oxide. The second film is placed on the first film and including mainly silicon nitride or silicon dioxide.

Abstract: A semiconductor memory device includes a substrate, a first stacked body provided in a first region on the substrate, a transistor formed in a second region of the substrate, and a block member provided between the first stacked body and the transistor. The first stacked body includes a plurality of first silicon oxide films and a plurality of electrode films stacked alternately one by one. Diffusion coefficient of hydrogen in the block member is lower than diffusion coefficient of hydrogen in silicon oxide.

Abstract: A semiconductor memory device includes a stacked body including a plurality of word lines; a semiconductor layer extending through the word lines; a memory cell provided at a part where the semiconductor layer crosses one of the word lines, the memory cell including a plurality of cell layers, the cell layers including a first insulating layer; and at least one of a first structural body and a second structural body provided around the stacked body. The first structural body includes a plurality of monitor layers including same materials respectively as materials of the cell layers. The second structural body includes a first electrode, a second electrode and an insulating body positioned between the first electrode and the second electrode. The insulating body includes same material as a material of the first insulating layer, and has almost the same thickness as a thickness of the first insulating layer.

Abstract: A semiconductor memory device includes a stacked body including a plurality of word lines; a semiconductor layer extending through the word lines; a memory cell provided at a part where the semiconductor layer crosses one of the word lines, the memory cell including a plurality of cell layers, the cell layers including a first insulating layer; and at least one of a first structural body and a second structural body provided around the stacked body. The first structural body includes a plurality of monitor layers including same materials respectively as materials of the cell layers. The second structural body includes a first electrode, a second electrode and an insulating body positioned between the first electrode and the second electrode. The insulating body includes same material as a material of the first insulating layer, and has almost the same thickness as a thickness of the first insulating layer.

Abstract: A semiconductor storage device according to an embodiment includes a plurality of memory cells, a first film, and a second film. The memory cells are placed at intervals in a first direction on a semiconductor substrate. The first film is placed continuously in the first direction above the memory cells so as to cover all of the memory cells and including mainly metal oxide. The second film is placed on the first film and including mainly silicon nitride or silicon dioxide.

Abstract: In accordance with an embodiment, a manufacturing method of a semiconductor device includes: forming memory cells and select transistors on a semiconductor substrate configured to select any memory cell, forming a first insulating nitride film, forming a contact, and selectively removing the first insulating nitride film. The first insulating nitride film is formed so as to cover the semiconductor substrate between the select transistors adjacent in the first direction, the select transistors, and the memory cells. The first insulating nitride film is selectively removed in a region other than the region in which the contact is formed and in a region above the select transistors or the memory cells.

Abstract: In accordance with an embodiment, a manufacturing method of a semiconductor device includes: forming memory cells and select transistors on a semiconductor substrate configured to select any memory cell, forming a first insulating nitride film, forming a contact, and selectively removing the first insulating nitride film. The first insulating nitride film is formed so as to cover the semiconductor substrate between the select transistors adjacent in the first direction, the select transistors, and the memory cells. The first insulating nitride film is selectively removed in a region other than the region in which the contact is formed and in a region above the select transistors or the memory cells.

Abstract: According to an embodiment, a semiconductor device includes a semiconductor element that is formed on a semiconductor substrate, an interlayer insulating film, including a silicon oxide film, that is formed to cover the semiconductor element, a wiring layer, including a metal, that is formed in the interlayer insulating film, and a first metal silicide film that is formed between the wiring layer and the interlayer insulating film.

Abstract: According to one embodiment, a semiconductor memory device includes a lower gate layer, a stacked body including a plurality of electrode layers and a plurality of insulating layers, alternately stacked on the lower gate layer, a channel body extending within the stacked body from the topmost electrode layer to the lower gate layer, and a memory film provided between the electrode layer and the channel body. The memory film includes a charge storage film. The electrode layer includes a step portion in which a step is formed in a stacking direction of the stacked body. The channel body and the memory film pass through the step portion.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes: a plurality of first semiconductor regions arranged each via a space in a direction crossing a first direction; a plurality of control gate electrodes; and a select gate electrode extending in a second direction, and the select gate electrode aligned with a control gate electrode located on an outermost side out of the plurality of control gate electrodes via the space; a first insulating layer covering the plurality of control gate electrodes and the select gate electrode, the first insulating layer provided on a side wall of the select gate electrode via the space, and a portion of the first insulating layer bridged between adjacent ones of the plurality of control gate electrodes protruding toward the space between adjacent ones of the plurality of control gate electrodes.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes: a plurality of first semiconductor regions arranged each via a space in a direction crossing a first direction; a plurality of control gate electrodes; and a select gate electrode extending in a second direction, and the select gate electrode aligned with a control gate electrode located on an outermost side out of the plurality of control gate electrodes via the space; a first insulating layer covering the plurality of control gate electrodes and the select gate electrode, the first insulating layer provided on a side wall of the select gate electrode via the space, and a portion of the first insulating layer bridged between adjacent ones of the plurality of control gate electrodes protruding toward the space between adjacent ones of the plurality of control gate electrodes.

Abstract: According to one embodiment, a semiconductor memory device includes a lower gate layer, a stacked body including a plurality of electrode layers and a plurality of insulating layers, alternately stacked on the lower gate layer, a channel body extending within the stacked body from the topmost electrode layer to the lower gate layer, and a memory film provided between the electrode layer and the channel body. The memory film includes a charge storage film. The electrode layer includes a step portion in which a step is formed in a stacking direction of the stacked body. The channel body and the memory film pass through the step portion.

Abstract: A semiconductor memory device comprising a stacked unit, a semiconductor pillar, a charge storage layer, and a non-insulating film. The stacked unit includes first conductive layers and first insulating layers which are stacked alternately. The semiconductor pillar passes through the stacked body and the semiconductor pillar has a tubular structure. The charge storage layer is provided between the semiconductor pillar and each of the first conductive layers. The non-insulating film is provided inside the tubular structure and has a non-insulating member. The first effective impurity concentration of the non-insulating film is lower than a second effective impurity concentration of the semiconductor pillar.

Abstract: According to one embodiment, a semiconductor device includes a stacked body, a second conductive layer, a second insulating layer, a tubular semiconductor pillar, an insulating film and an occlusion film. The second conductive layer is provided on the stacked body. The second insulating layer is provided on the second conductive layer. The tubular semiconductor pillar is provided in such a manner as to pass through the second insulating layer, the second conductive layer and the stacked body. The insulating film is provided between the semiconductor pillar, and the second insulating layer, the second conductive layer and the stacked body. The occlusion film occludes the tube in a lower portion of the portion passing through the second insulating layer in the semiconductor pillar. The tube below the occlusion film in the semiconductor pillar is an air gap.

Abstract: According to one embodiment, a method of manufacturing a semiconductor device including a memory cell transistor in a first region of a substrate and a select gate transistor in a second region of the substrate includes: forming a gate insulating film, a lower gate electrode, an inter-electrode insulating film, an upper gate electrode, and a hard mask on the substrate; forming a groove passing through the hard mask, the upper gate electrode, and the inter-electrode insulating film and reaching the lower gate electrode in the second region; and forming a connection layer having a crystal structure which preferentially has a specific crystal orientation and that electrically connects between the lower gate electrode and the upper gate electrode by being selectively crystal-grown while being subjected to an influence from a crystal structure of the lower gate electrode in the groove