Patents by Inventor Nobuhito Ogata

Nobuhito Ogata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device including capacitor with lower electrode including iridium and iridium oxide layers
    Patent number: 6608383
    Abstract: A semiconductor memory device includes: a capacitor formed on a substrate and including a lower electrode, a dielectric film and an upper electrode; a selection transistor formed at the substrate; an electrically conductive plug for providing electrical connection between the selection transistor and the capacitor; and a diffusion barrier film provided between the electrically conductive plug and the lower electrode of the capacitor. The diffusion barrier film is a TaxSi1−xNy film or a HfxSi1−xNy film (where 0.2<x<1 and 0<y<1). The lower electrode includes an Ir film and an IrO2 film which are sequentially formed.
    Type: Grant
    Filed: September 13, 2001
    Date of Patent: August 19, 2003
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Seiichi Yokoyama, Shun Mitarai, Masaya Nagata, Jun Kudo, Nobuhito Ogata, Yasuyuki Itoh
  • Semiconductor memory device and production method of the same
    Publication number: 20020003247
    Abstract: A semiconductor memory device includes: a capacitor formed on a substrate and including a lower electrode, a dielectric film and an upper electrode; a selection transistor formed at the substrate; an electrically conductive plug for providing electrical connection between the selection transistor and the capacitor; and a diffusion barrier film provided between the electrically conductive plug and the lower electrode of the capacitor. The diffusion barrier film is a TaxSi1−xNy film or a HfxSi1−xNy film (where 0.2<x<1 and 0<y<1). The lower electrode includes an Ir film and an IrO2 film which are sequentially formed.
    Type: Application
    Filed: September 13, 2001
    Publication date: January 10, 2002
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Seiichi Yokoyama, Shun Mitarai, Masaya Nagata, Jun Kudo, Nobuhito Ogata, Yasuyuki Itoh
  • Semiconductor memory device and production method of the same
    Patent number: 6313539
    Abstract: A semiconductor memory device includes: a capacitor formed on a substrate and including a lower electrode, a dielectric film and an upper electrode; a selection transistor formed at the substrate; an electrically conductive plug for providing electrical connection between the selection transistor and the capacitor; and a diffusion barrier film provided between the electrically conductive plug and the lower electrode of the capacitor. The diffusion barrier film is a TaxSi1−xNy film or a HfxSi1−xNy film (where 0.2<x<1 and 0<y<1). The lower electrode includes an Ir film and an IrO2 film which are sequentially formed.
    Type: Grant
    Filed: December 23, 1998
    Date of Patent: November 6, 2001
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Seiichi Yokoyama, Shun Mitarai, Masaya Nagata, Jun Kudo, Nobuhito Ogata, Yasuyuki Itoh
  • Methods for fabricating a semiconductor memory device including flattening of a capacitor dielectric film
    Patent number: 6232174
    Abstract: In a method for fabrication a semiconductor memory device which has a capacitor having a lower electrode, a dielectric film and an upper electrode stacked in this order, after the dielectric film is formed to a desired film thickness, the dielectric film is flattened by removing the dielectric film by a specified amount.
    Type: Grant
    Filed: December 1, 1999
    Date of Patent: May 15, 2001
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Masaya Nagata, Nobuhito Ogata, Kazuya Ishihara, Jun Kudo