Patents by Inventor Nobukazu Koizumi

Nobukazu Koizumi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240063997
    Abstract: A phase compensation device configured to compensate phase of a received signal obtained by photoelectrically converting a phase-modulated optical signal, the phase compensation device includes a processor configured to: detect whether reversal of a phase of the received signal is present, based on a known signal contained in the received signal; compensate the phase of the received signal, based on whether reversal of the phase is detected; and after compensating the phase, compensate reversal of the phase of the received signal, based on whether reversal of the phase is detected.
    Type: Application
    Filed: June 26, 2023
    Publication date: February 22, 2024
    Applicant: Fujitsu Limited
    Inventors: Yoshitaka NOMURA, Hisao NAKASHIMA, Nobukazu KOIZUMI
  • Patent number: 11476946
    Abstract: A signal processing device includes: a memory; and a processor coupled to the memory and configured to: compensate an electric field signal representing an electric field component in an optical signal input from a transmission channel for an optical frequency offset between light sources on a transmission side and a reception side of the optical signal based on a compensation value; calculate an estimated value of the optical frequency offset from data having a fixed pattern in the electric field signal; generate a plurality of candidates for the compensation value from the estimated value; calculate power of the optical signal compensated for the optical frequency offset based on each of the plurality of candidates; and select an initial value of the compensation value from the plurality of candidates based on the power of the optical signal.
    Type: Grant
    Filed: December 17, 2021
    Date of Patent: October 18, 2022
    Assignee: FUJITSU LIMITED
    Inventors: Yoshitaka Nomura, Hisao Nakashima, Nobukazu Koizumi, Daisuke Sasaki, Yasuo Ohtomo
  • Publication number: 20220303021
    Abstract: A signal processing device includes: a memory; and a processor coupled to the memory and configured to: compensate an electric field signal representing an electric field component in an optical signal input from a transmission channel for an optical frequency offset between light sources on a transmission side and a reception side of the optical signal based on a compensation value; calculate an estimated value of the optical frequency offset from data having a fixed pattern in the electric field signal; generate a plurality of candidates for the compensation value from the estimated value; calculate power of the optical signal compensated for the optical frequency offset based on each of the plurality of candidates; and select an initial value of the compensation value from the plurality of candidates based on the power of the optical signal.
    Type: Application
    Filed: December 17, 2021
    Publication date: September 22, 2022
    Applicant: FUJITSU LIMITED
    Inventors: Yoshitaka Nomura, Hisao Nakashima, Nobukazu KOIZUMI, Daisuke SASAKI, Yasuo OHTOMO
  • Patent number: 11159352
    Abstract: An adaptive equalizer includes a sample buffer that temporarily stores data obtained by fractional sampling at a sampling rate that is larger than one time and smaller than two times a symbol rate; and a processor coupled to the sample buffer and configured to: specify position of a training sequence in the data based on a correlation value between a first set of (f×T) samples and a second set of (f×T) samples following the first set of samples, assuming that the sampling rate is f, and a symbol length of a code pattern included in the training sequence inserted in the data is T, and calculate an initial value of a tap coefficient set to a tap of an adaptive equalization filter based on the specified training sequence, wherein the symbol length is set to be changeable so that f×T is an integer.
    Type: Grant
    Filed: October 9, 2020
    Date of Patent: October 26, 2021
    Assignee: FUJITSU LIMITED
    Inventors: Daisuke Sasaki, Hisao Nakashima, Nobukazu Koizumi
  • Patent number: 11146428
    Abstract: An adaptive equalizer, includes a sample buffer; and a processor coupled to the sample buffer and configured to: perform an adaptive equalization on data which has been fractionally sampled at a sampling rate higher than once a symbol rate and lower than twice the symbol rate, determine an initial value of a tap coefficient of the adaptive equalizer by using a training sequence inserted in the data, shift, by a predetermined shift amount, a sample point of one pattern from among two consecutive patterns included in the training sequence, specify a position of the training sequence in the data by replacing an original sample value with a sample value at the shifted sample point, and update the initial value of the tap coefficient based on the specified training sequence.
    Type: Grant
    Filed: October 19, 2020
    Date of Patent: October 12, 2021
    Assignee: FUJITSU LIMITED
    Inventors: Daisuke Sasaki, Hisao Nakashima, Nobukazu Koizumi
  • Publication number: 20210160108
    Abstract: An adaptive equalizer includes a sample buffer that temporarily stores data obtained by fractional sampling at a sampling rate that is larger than one time and smaller than two times a symbol rate; and a processor coupled to the sample buffer and configured to: specify position of a training sequence in the data based on a correlation value between a first set of (f×T) samples and a second set of (f×T) samples following the first set of samples, assuming that the sampling rate is f, and a symbol length of a code pattern included in the training sequence inserted in the data is T, and calculate an initial value of a tap coefficient set to a tap of an adaptive equalization filter based on the specified training sequence, wherein the symbol length is set to be changeable so that f×T is an integer.
    Type: Application
    Filed: October 9, 2020
    Publication date: May 27, 2021
    Applicant: FUJITSU LIMITED
    Inventors: Daisuke SASAKI, Hisao Nakashima, Nobukazu KOIZUMI
  • Publication number: 20210152403
    Abstract: An adaptive equalizer, includes a sample buffer; and a processor coupled to the sample buffer and configured to: perform an adaptive equalization on data which has been fractionally sampled at a sampling rate higher than once a symbol rate and lower than twice the symbol rate, determine an initial value of a tap coefficient of the adaptive equalizer by using a training sequence inserted in the data, shift, by a predetermined shift amount, a sample point of one pattern from among two consecutive patterns included in the training sequence, specify a position of the training sequence in the data by replacing an original sample value with a sample value at the shifted sample point, and update the initial value of the tap coefficient based on the specified training sequence.
    Type: Application
    Filed: October 19, 2020
    Publication date: May 20, 2021
    Applicant: FUJITSU LIMITED
    Inventors: Daisuke SASAKI, Hisao Nakashima, Nobukazu KOIZUMI
  • Patent number: 10931485
    Abstract: An adaptive equalization circuit includes: a first filter configure to perform filtering on an input signal based on a tap coefficient; an applying circuit configured to apply, to the signal, noise outside a band of the signal; and a controller configured to set, for the first filter, the tap coefficient that compensates for transmission line characteristics of the signal, based on the signal to which the noise is applied by the applying circuit.
    Type: Grant
    Filed: January 3, 2020
    Date of Patent: February 23, 2021
    Assignee: FUJITSU LIMITED
    Inventors: Yuya Imoto, Kazuhiko Hatae, Nobukazu Koizumi, Yasuo Ohtomo, Masashi Sato, Daisuke Sasaki
  • Publication number: 20200267030
    Abstract: An adaptive equalization circuit includes: a first filter configure to perform filtering on an input signal based on a tap coefficient; an applying circuit configured to apply, to the signal, noise outside a band of the signal; and a controller configured to set, for the first filter, the tap coefficient that compensates for transmission line characteristics of the signal, based on the signal to which the noise is applied by the applying circuit.
    Type: Application
    Filed: January 3, 2020
    Publication date: August 20, 2020
    Applicant: FUJITSU LIMITED
    Inventors: Yuya IMOTO, KAZUHIKO HATAE, Nobukazu KOIZUMI, Yasuo OHTOMO, Masashi Sato, Daisuke SASAKI
  • Patent number: 10560199
    Abstract: A signal processing circuit includes: a processor configured to adjust phases of reception samples which is supplied at a supply interval, according to a phase adjustment amount; and a processing circuit including a finite impulse response (FIR) filter with taps and configured to process, by the FIR filter, each of the reception samples and output output symbols at an output interval different from the supply interval, the processor is configured to: derive initial values of tap coefficients for the respective taps; and derive the phase adjustment amount such that a center of centroids of the tap coefficients at respective output time points of the output symbols coincides with a center of a number of taps of the FIR filter, the tap coefficients at respective output time points of the output symbols being set according to a deviation between the supply interval and the output interval and the initial values.
    Type: Grant
    Filed: January 24, 2019
    Date of Patent: February 11, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Yuya Imoto, Kazuhiko Hatae, Nobukazu Koizumi, Yasuo Ohtomo, Masato Oota, Masashi Sato, Daisuke Sasaki
  • Publication number: 20190280779
    Abstract: A signal processing circuit includes: a processor configured to adjust phases of reception samples which is supplied at a supply interval, according to a phase adjustment amount; and a processing circuit including a finite impulse response (FIR) filter with taps and configured to process, by the FIR filter, each of the reception samples and output output symbols at an output interval different from the supply interval, the processor is configured to: derive initial values of tap coefficients for the respective taps; and derive the phase adjustment amount such that a center of centroids of the tap coefficients at respective output time points of the output symbols coincides with a center of a number of taps of the FIR filter, the tap coefficients at respective output time points of the output symbols being set according to a deviation between the supply interval and the output interval and the initial values.
    Type: Application
    Filed: January 24, 2019
    Publication date: September 12, 2019
    Applicant: FUJITSU LIMITED
    Inventors: Yuya IMOTO, KAZUHIKO HATAE, Nobukazu KOIZUMI, Yasuo OHTOMO, Masato OOTA, Masashi Sato, Daisuke SASAKI
  • Patent number: 10177855
    Abstract: An amplitude adjustment circuit includes a memory that stores correspondence information between frequency distributions of an amplitude and adjustment coefficients, a processor configured to generate a frequency distribution of amplitude of data for which adaptive equalization processing has been executed, acquire the correspondence information between frequency distributions of the amplitude and adjustment coefficients from the memory, select the adjustment coefficient based on a result of comparison between the frequency distributions included in the correspondence information acquired by the acquiring unit and the frequency distribution generated by the generating unit, and adjust a gain of the data based on the adjustment coefficient selected by the selecting unit.
    Type: Grant
    Filed: October 6, 2017
    Date of Patent: January 8, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Masashi Sato, Kazuhiko Hatae, Nobukazu Koizumi, Yasuo Ohtomo, Masato Oota, Daisuke Sasaki, Yuya Imoto
  • Publication number: 20180123701
    Abstract: An amplitude adjustment circuit includes a memory that stores correspondence information between frequency distributions of an amplitude and adjustment coefficients, a processor configured to generate a frequency distribution of amplitude of data for which adaptive equalization processing has been executed, acquire the correspondence information between frequency distributions of the amplitude and adjustment coefficients from the memory, select the adjustment coefficient based on a result of comparison between the frequency distributions included in the correspondence information acquired by the acquiring unit and the frequency distribution generated by the generating unit, and adjust a gain of the data based on the adjustment coefficient selected by the selecting unit.
    Type: Application
    Filed: October 6, 2017
    Publication date: May 3, 2018
    Applicant: FUJITSU LIMITED
    Inventors: Masashi Sato, KAZUHIKO HATAE, Nobukazu KOIZUMI, Yasuo OHTOMO, Masato OOTA, Daisuke SASAKI, Yuya IMOTO
  • Patent number: 9680667
    Abstract: A circuit includes a calculation circuit configured to calculate a noise power of a predetermined-training-sequence pattern repeatedly included in a first signal input into an adaptive equalizer, based on a second signal obtained by compensating the first signal by a compensation circuit, a channel-estimation value based on the second signal, and the predetermined-training-sequence pattern; and an average circuit configured to obtain an average value of estimation values of frequency offsets based on the predetermined-training-sequence pattern having the noise power equal to or smaller than a predetermined power, among estimation values of frequency offsets based on the predetermined-training-sequence pattern, wherein the compensation circuit is configured to compensate a frequency offset of the predetermined-training sequence pattern based on the average value and thereby obtain the second signal, and the adaptive equalizer is configured to perform adaptive-equalization processing of the first signal with a
    Type: Grant
    Filed: July 6, 2016
    Date of Patent: June 13, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Daisuke Sasaki, Kazuhiko Hatae, Tomoki Katou, Nobukazu Koizumi, Masato Oota, Yasuo Ohtomo, Manabu Yamazaki, Masashi Sato
  • Patent number: 9660733
    Abstract: A signal processing apparatus includes: a filter; and a filter control circuit, wherein the filter control circuit is configured to: detect a power of signals output from the filter; determine one of a plurality of numerical ranges to which the power belongs; update a filter coefficient of the filter according to a determination result; count a number of the signals having the power of a first value or more; set an invalid area which becomes a target not to be determined for each of one or more boundaries between the plurality of numerical ranges when the number of the signals becomes a second value or more; and control a width of the invalid area based on the number of signals.
    Type: Grant
    Filed: September 1, 2015
    Date of Patent: May 23, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Masashi Sato, Kazuhiko Hatae, Tomoki Katou, Nobukazu Koizumi, Masato Oota, Yasuo Ohtomo, Manabu Yamazaki, Daisuke Sasaki
  • Publication number: 20170012803
    Abstract: A circuit includes a calculation circuit configured to calculate a noise power of a predetermined-training-sequence pattern repeatedly included in a first signal input into an adaptive equalizer, based on a second signal obtained by compensating the first signal by a compensation circuit, a channel-estimation value based on the second signal, and the predetermined-training-sequence pattern; and an average circuit configured to obtain an average value of estimation values of frequency offsets based on the predetermined-training-sequence pattern having the noise power equal to or smaller than a predetermined power, among estimation values of frequency offsets based on the predetermined-training-sequence pattern, wherein the compensation circuit is configured to compensate a frequency offset of the predetermined-training sequence pattern based on the average value and thereby obtain the second signal, and the adaptive equalizer is configured to perform adaptive-equalization processing of the first signal with a
    Type: Application
    Filed: July 6, 2016
    Publication date: January 12, 2017
    Applicant: FUJITSU LIMITED
    Inventors: Daisuke SASAKI, KAZUHIKO HATAE, TOMOKI KATOU, Nobukazu KOIZUMI, Masato OOTA, Yasuo OHTOMO, MANABU YAMAZAKI, Masashi Sato
  • Patent number: 9496966
    Abstract: A receiving device that converts, to a digital signal, a signal in which signal light from an optical transmission path and local oscillation light are mixed, so as to perform digital signal processing, the optical communication receiving device comprising: a frequency offset compensation unit configured to calculate a frequency offset of the digital signal and to, based on the frequency offset, compensate for a phase of the digital signal; a carrier phase recovery unit configured to calculate a carrier phase of the digital signal whose phase is compensated for in the frequency offset compensation unit; and a residual frequency offset detection unit configured to calculate an average of differences in the carrier phase, and to output the average as a residual frequency offset, wherein the frequency offset compensation unit is configured to correct the frequency offset using the residual frequency offset output by the residual frequency offset detection unit.
    Type: Grant
    Filed: September 24, 2014
    Date of Patent: November 15, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Kazuhiko Hatae, Nobukazu Koizumi, Koji Nakamuta, Manabu Yamazaki, Tomoki Katou, Masashi Sato, Hisao Nakashima
  • Patent number: 9444554
    Abstract: A digital coherent receiving apparatus includes a first oscillator for outputting a local light signal of a fixed frequency, a hybrid unit mixing the local light signal with a light signal received by a receiver, a second oscillator for outputting a sampling signal of a sampling frequency, a converter for converting the mixed light signal into digital signal synchronizing with the sampling signal, a waveform adjuster for adjusting a waveform distortion of the converted digital signal, a phase adjustor for adjusting a phase of the digital signal adjusted by the waveform adjustor, a demodulator for demodulating the digital signal adjusted by the phase adjuster, and a phase detector for detecting a phase of the digital signal adjusted by the phase adjuster, and a control signal output unit for outputting a frequency control signal on the basis of the detected phase signal to the second oscillator.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: September 13, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Nobukazu Koizumi, Takeshi Hoshida, Takahito Tanimura, Hisao Nakashima, Koji Nakamuta, Noriyasu Nakayama
  • Patent number: 9407471
    Abstract: A method of tap coefficient correction includes: obtaining a synchronization symbol difference between a first polarization and a second polarization orthogonal to the first polarization; obtaining a delay amount of each of the first polarization and the second polarization in an adaptive equalizer; calculating, in a case where a horizontal axis represents a tap number and a vertical axis represents a tap coefficient and a tap number or a nearest tap number with which an area of a drawn figure is halved is set as a gravity center of tap coefficients, a correction reference gravity center of the tap coefficients set in the adaptive equalizer, based on the synchronization symbol difference and the delay amount; and performing a correction of shifting an entire tap coefficients in units of symbol to cause the correction reference gravity center to be closest to a tap center.
    Type: Grant
    Filed: November 18, 2013
    Date of Patent: August 2, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Taku Saito, Nobukazu Koizumi, Hisao Nakashima, Osamu Takeuchi, Hirofumi Araki
  • Publication number: 20160134261
    Abstract: A signal processing apparatus includes: a filter; and a filter control circuit, wherein the filter control circuit is configured to: detect a power of signals output from the filter; determine one of a plurality of numerical ranges to which the power belongs; update a filter coefficient of the filter according to a determination result; count a number of the signals having the power of a first value or more; set an invalid area which becomes a target not to be determined for each of one or more boundaries between the plurality of numerical ranges when the number of the signals becomes a second value or more; and control a width of the invalid area based on the number of signals.
    Type: Application
    Filed: September 1, 2015
    Publication date: May 12, 2016
    Inventors: Masashi Sato, KAZUHIKO HATAE, TOMOKI KATOU, Nobukazu KOIZUMI, Masato OOTA, Yasuo OHTOMO, MANABU YAMAZAKI, Daisuke SASAKI