Patents by Inventor Nobuki KANREI

Nobuki KANREI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11075305
    Abstract: According to one embodiment, the oxide semiconductor layer contains at least one of indium (In) and tin (Sn). The insulating film is provided between the control electrode and the oxide semiconductor layer, and contains silicon oxide. The metal oxide film is provided between the insulating film and the oxide semiconductor layer, and contacts the insulating film and the oxide semiconductor layer. The metal oxide film contains at least one selected from a group consisting of gallium (Ga), tungsten (W), germanium (Ge), aluminum (Al), molybdenum (Mo), and titanium (Ti).
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: July 27, 2021
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Nobuki Kanrei
  • Patent number: 10930744
    Abstract: According to one embodiment, a semiconductor device includes an oxide semiconductor layer, a first electrode, a second electrode, and a control electrode. The oxide semiconductor layer includes tin and tungsten. An average coordination number of oxygen atoms to tin atoms is greater than 3 but less than 4. The first electrode is electrically connected to a first end portion of the oxide semiconductor layer. The second electrode is electrically connected to a second end portion of the oxide semiconductor layer on a side opposite to the first end portion. The control electrode opposes a portion of the oxide semiconductor layer between the first end portion and the second end portion.
    Type: Grant
    Filed: March 19, 2019
    Date of Patent: February 23, 2021
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA MEMORY CORPORATION
    Inventor: Nobuki Kanrei
  • Publication number: 20200098873
    Abstract: According to one embodiment, a semiconductor device includes an oxide semiconductor layer, a first electrode, a second electrode, and a control electrode. The oxide semiconductor layer includes tin and tungsten. An average coordination number of oxygen atoms to tin atoms is greater than 3 but less than 4. The first electrode is electrically connected to a first end portion of the oxide semiconductor layer. The second electrode is electrically connected to a second end portion of the oxide semiconductor layer on a side opposite to the first end portion. The control electrode opposes a portion of the oxide semiconductor layer between the first end portion and the second end portion.
    Type: Application
    Filed: March 19, 2019
    Publication date: March 26, 2020
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA MEMORY CORPORATION
    Inventor: Nobuki KANREI
  • Patent number: 10446651
    Abstract: According to one embodiment, an oxide semiconductor includes indium (In), gallium (Ga), and silicon (Si). A composition ratio of Si to In (Si/In) in the oxide semiconductor is larger than 0.2, and a composition ratio of Si to Ga (Si/Ga) in the oxide semiconductor is larger than 0.2.
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: October 15, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Nobuki Kanrei, Hisayo Momose
  • Publication number: 20190088795
    Abstract: According to one embodiment, the oxide semiconductor layer contains at least one of indium (In) and tin (Sn). The insulating film is provided between the control electrode and the oxide semiconductor layer, and contains silicon oxide. The metal oxide film is provided between the insulating film and the oxide semiconductor layer, and contacts the insulating film and the oxide semiconductor layer. The metal oxide film contains at least one selected from a group consisting of gallium (Ga), tungsten (W), germanium (Ge), aluminum (Al), molybdenum (Mo), and titanium (Ti).
    Type: Application
    Filed: August 29, 2018
    Publication date: March 21, 2019
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Nobuki Kanrei
  • Publication number: 20180076292
    Abstract: According to one embodiment, an oxide semiconductor includes indium (In), gallium (Ga), and silicon (Si). A composition ratio of Si to In (Si/In) in the oxide semiconductor is larger than 0.2, and a composition ratio of Si to Ga (Si/Ga) in the oxide semiconductor is larger than 0.2.
    Type: Application
    Filed: September 7, 2017
    Publication date: March 15, 2018
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Nobuki KANREI, Hisayo MOMOSE
  • Publication number: 20160380115
    Abstract: A thin film transistor includes semiconductor layer, source electrode, and drain electrode. The semiconductor layer includes first to fifth regions. The third region is provided between the first and second regions. The first region is disposed between the fourth and third regions. The second region is disposed between the fifth and third regions. The semiconductor layer includes an oxide. The source electrode is connected to the first region. The drain electrode is connected to the second region. First thickness of the first region along a second direction is thinner than third thickness along the second direction of each of the third to fifth regions. The second direction crosses a first direction and connects the first region and the source electrode. The first direction connects the first and second regions. Second thickness of the second region along the second direction is thinner than the third thickness.
    Type: Application
    Filed: September 7, 2016
    Publication date: December 29, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Shintaro NAKANO, Yuya MAEDA, Tatsuya OHGURO, Hisayo MOMOSE, Tetsu MOROOKA, Kazuya FUKASE, Nobuki KANREI
  • Publication number: 20160093742
    Abstract: A semiconductor device according to an embodiment, includes a gate electrode, a first dielectric film, a first oxide semiconductor film, a second dielectric film, a source electrode, a source wire, a drain electrode, and a drain wire. The source wire is arranged on the second dielectric film, and connected to the source electrode. The drain wire is arranged on the second dielectric film, and connected to the drain electrode. At least one of the source wire and the drain wire includes a fringe portion sticking out above a channel region. A barrier film that suppresses intrusion of hydrogen is arranged being in contact with at least one of an upper surface and a lower surface of the fringe portion. A region where the barrier film is not formed is included above the channel region.
    Type: Application
    Filed: March 19, 2015
    Publication date: March 31, 2016
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hisayo MOMOSE, Tatsuya OHGURO, Tetsu MOROOKA, Kazuya FUKASE, Shintaro NAKANO, Yuya MAEDA, Shuichi TORIYAMA, Nobuki KANREI
  • Publication number: 20140264688
    Abstract: According to one embodiment, a solid state imaging device includes a silicon substrate unit, a color filter layer, first, second and third optical layers. The silicon substrate unit includes imaging units provided in a plane parallel to a major surface. The color filter layer is apart from the silicon substrate unit. The color filter has a lower refractive index than the silicon substrate unit. The first optical layer has a lower first refractive index than the color filter layer and the silicon substrate unit, and is light transmissive. The second optical layer has a second refractive index higher than the first refractive index and lower than the refractive index of the silicon substrate unit, is light transmissive. The third optical layer has a third refractive index lower than the refractive index of the color filter layer and lower than the second refractive index, and is light transmissive.
    Type: Application
    Filed: September 11, 2013
    Publication date: September 18, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Nobuki KANREI