Abstract: A method of manufacturing a semiconductor device includes in a following order: a first forming step where a gate electrode is formed on a first main surface side of a semiconductor base substrate with a gate insulation film interposed therebetween and, thereafter, an interlayer insulation film is formed to cover the gate electrode; a second forming step where a metal layer in a state of being connected with the gate electrode is formed over the interlayer insulation film; an irradiating step where a lattice defect is formed inside the semiconductor base substrate by irradiating an electron beam to the semiconductor base substrate in a state where the metal layer is set to a ground potential; a dividing step where the metal layer is divided into a plurality of electrodes; and an annealing step where the lattice defect in the semiconductor base substrate is repaired by heating the semiconductor base substrate.

Abstract: A method of manufacturing a semiconductor device includes in a following order: a first forming step where a gate electrode is formed on a first main surface side of a semiconductor base substrate with a gate insulation film interposed therebetween and, thereafter, an interlayer insulation film is formed to cover the gate electrode; a second forming step where a metal layer in a state of being connected with the gate electrode is formed over the interlayer insulation film; an irradiating step where a lattice defect is formed inside the semiconductor base substrate by irradiating an electron beam to the semiconductor base substrate in a state where the metal layer is set to a ground potential; a dividing step where the metal layer is divided into a plurality of electrodes; and an annealing step where the lattice defect in the semiconductor base substrate is repaired by heating the semiconductor base substrate.

Abstract: In a semiconductor device provided with a MOSFET part and a gate pad part defined on a semiconductor substrate which is formed by laminating a low resistance semiconductor layer and a drift layer, the gate pad part includes: the low resistance semiconductor layer; the drift layer formed on the low resistance semiconductor layer; a poly-silicon layer constituting a conductor layer and a gate pad electrode formed above the drift layer over the whole area of the gate pad part with a field insulation layer interposed therebetween; and a gate oscillation suppressing structure where a p-type diffusion region electrically connected with the a source electrode layer and a p-type impurity non-diffusion region are alternately formed on a surface of the drift layer.

Abstract: In a semiconductor device provided with a MOSFET part and a gate pad part, the gate pad part includes: a low resistance semiconductor layer; a drift layer; a poly-silicon layer constituting a conductor layer and a gate pad electrode formed above the drift layer over the whole area of the gate pad part with a field insulation layer interposed therebetween; and a gate oscillation suppressing structure, wherein the gate oscillation suppressing structure includes a p+-type diffusion region which is disposed along an outer peripheral portion of the gate pad part and is electrically connected with the a source electrode layer, and a p+-type diffusion region in a floating state and the p-type impurity non-diffusion regions which are alternately formed in the region surrounded by the p+-type diffusion region.

Abstract: In a semiconductor device provided with a MOSFET part and a gate pad part, the gate pad part includes: a low resistance semiconductor layer; a drift layer; a poly-silicon layer constituting a conductor layer and a gate pad electrode formed above the drift layer over the whole area of the gate pad part with a field insulation layer interposed therebetween; and a gate oscillation suppressing structure, wherein the gate oscillation suppressing structure includes a p+-type diffusion region which is disposed along an outer peripheral portion of the gate pad part and is electrically connected with the a source electrode layer, and a p+-type diffusion region in a floating state and the p-type impurity non-diffusion regions which are alternately formed in the region surrounded by the p+-type diffusion region.

Abstract: A semiconductor device includes, in a cell region thereof: a low resistance semiconductor layer; a drift layer; a base region; a high-concentration semiconductor region; and a gate electrode layer. The semiconductor device includes, in a peripheral region thereof: the low resistance semiconductor layer; the drift layer; which is formed over the low resistance semiconductor layer; a gate lead line; a gate finger; and a gate pad. The gate electrode layer and the gate lead line are electrically connected with each other by way of a resistor made of polysilicon containing an impurity, and an impurity concentration in polysilicon which forms the resistor is lower than an impurity concentration in polysilicon which forms the gate electrode layer.

Abstract: In a semiconductor device provided with a MOSFET part and a gate pad part defined on a semiconductor substrate which is formed by laminating a low resistance semiconductor layer and a drift layer, the gate pad part includes: the low resistance semiconductor layer; the drift layer formed on the low resistance semiconductor layer; a poly-silicon layer constituting a conductor layer and a gate pad electrode formed above the drift layer over the whole area of the gate pad part with a field insulation layer interposed therebetween; and a gate oscillation suppressing structure where a p-type diffusion region electrically connected with the a source electrode layer and a p-type impurity non-diffusion region are alternately formed on a surface of the drift layer.

Abstract: A semiconductor device includes, in a cell region thereof: a low resistance semiconductor layer; a drift layer; a base region; a high-concentration semiconductor region; and a gate electrode layer. The semiconductor device includes, in a peripheral region thereof: the low resistance semiconductor layer; the drift layer; which is formed over the low resistance semiconductor layer; a gate lead line; a gate finger; and a gate pad. The gate electrode layer and the gate lead line are electrically connected with each other by way of a resistor made of polysilicon containing an impurity, and an impurity concentration in polysilicon which forms the resistor is lower than an impurity concentration in polysilicon which forms the gate electrode layer.

Abstract: A semiconductor device including a plurality of units having identical structures, each unit includes: a drain electrode; a drift layer that includes a low concentration layer on the drain electrode and a reference concentration layer on the low concentration layer, a gate electrode on the reference concentration layer; a pair of source regions that are provided on an upper surface of the reference concentration layer and in the vicinity of both ends of the gate electrode; a pair of base regions that surround outer surfaces of the source regions; a source electrode electrically connected to the source regions and the base regions; and a pair of depletion-layer extension regions that are respectively provided under the base regions in the reference concentration region. Boundaries between the depletion-layer extension regions and the low concentration layer are positioned lower than a boundary between the reference concentration layer and the low concentration layer.

Abstract: A semiconductor device (10) of the present invention includes: a drift layer (5) that includes a reference concentration layer (4) including an impurity of a first conductive type at a first reference concentration and a low concentration layer (3) provided under the reference concentration layer and including an impurity of the first conductive type at a concentration lower than the first reference concentration; a gate electrode (20) that is formed on an upper surface of the reference concentration layer; a pair of source regions (Sa and 8b) that are respectively provided on the reference concentration layer in the vicinity of ends of the gate electrode and include an impurity of the first conductive type at a concentration higher than the first reference concentration.

Abstract: A semiconductor device including a plurality of units having identical structures, each unit includes: a drain electrode; a drift layer that includes a low concentration layer on the drain electrode and a reference concentration layer on the low concentration layer, a gate electrode on the reference concentration layer; a pair of source regions that are provided on an upper surface of the reference concentration layer and in the vicinity of both ends of the gate electrode; a pair of base regions that surround outer surfaces of the source regions; a source electrode electrically connected to the source regions and the base regions; and a pair of depletion-layer extension regions that are respectively provided under the base regions in the reference concentration region. Boundaries between the depletion-layer extension regions and the low concentration layer are positioned lower than a boundary between the reference concentration layer and the low concentration layer.

Abstract: A semiconductor device (10) of the present invention includes: a drift layer (5) that includes a reference concentration layer (4) including an impurity of a first conductive type at a first reference concentration and a low concentration layer (3) provided under the reference concentration layer and including an impurity of the first conductive type at a concentration lower than the first reference concentration; a gate electrode (20) that is formed on an upper surface of the reference concentration layer; a pair of source regions (8a and 8b) that are respectively provided on the reference concentration layer in the vicinity of ends of the gate electrode and include an impurity of the first conductive type at a concentration higher than the first reference concentration; a pair of base regions (7a and 7b) that respectively surround outer surfaces of diffusion layers of the source regions and include an impurity of the second conductive type at a second reference concentration; a source electrode (14) that is

Abstract: A field effect transistor with a high withstand voltage and a low resistance is provided. A ring-shaped channel region is disposed inside a source region formed in a ring, and the inside of the channel region is taken as a drain region. A depletion layer extends toward the inside of the drain region, resulting in a high withstand voltage. In the portion, except the portion within a prescribed distance from the corner portion of the channel region, a low resistance conductive layer is disposed, thereby resulting in high withstand voltage.

Abstract: A highly conductive region 18 serving as a surface of a drain layer 2 of a first conductivity type is diffused more deeply than a main diffused layer 36 and a diffused channel layer 37, and has a small conducting resistance. The highly conductive region 18 is surrounded by a diffused region 40 of a second conductivity type which comprises a diffused base layer 38 and a diffused guard ring layer 13. Therefore, the highly conductive region 18 does not form spherical junctions, and a depletion layer spreading in the highly conductive region 18 extends into the highly conductive region 18. The highly conductive region 18 thus has a high withstand voltage while maintaining the low conducting resistance.

Abstract: A field effect transistor having a high breakdown withstand capacity is provided. An active region 7a is surrounded by a fixed potential diffusion layer 16, and a channel region 15 is formed in the active region 7a. A gate pad 35 is provided outside the fixed potential diffusion layer 16. Minority carriers injected at a peripheral region of the active region 7a flow into the fixed potential diffusion layer 16, which prevents breakdown attributable to concentration of the carriers. The fixed potential diffusion layer 16 is surrounded by a plurality of guard ring diffusion layers 171 through 174, and a pad diffusion layer 18 formed in a position under the gate pad 35 is connected to the innermost guard ring diffusion layer 171. Since this encourages expansion of a depletion layer under the gate pad 35, an increased breakdown voltage is provided.

Abstract: A field effect transistor with a high withstand voltage and a low resistance is provided. A ring-shaped channel region is disposed inside a source region formed in a ring, and the inside of the channel region is taken as a drain region. A depletion layer extends toward the inside of the drain region, resulting in a high withstand voltage. In the portion, except the portion within a prescribed distance from the corner portion of the channel region, a low resistance conductive layer is disposed, thereby resulting in high withstand voltage.