Patents by Inventor Nobuki Tominaga

Nobuki Tominaga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9020241
    Abstract: A image providing device provides a user with realistic and natural past-experience simulation through stereoscopic photographs. Specifically, feature-point extractors extract feature points from a foreground image and a background image, respectively. A stereoscopic matching module searches for pairs of feature points matching between the foreground image and the background image and obtains using the feature point pairs a transformation matrix for projecting the foreground image onto the background image. The transformation by the transformation matrix obtained by the matching unit is applied to foreground depth data, which is depth data of the foreground image. Lastly, depth based rendering is performed based on the transformed foreground depth data to obtain two or more viewpoint images corresponding to the foreground image.
    Type: Grant
    Filed: February 29, 2012
    Date of Patent: April 28, 2015
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Germano Leichsenring, Tomoko Katayama, Hidetaka Oto, Nobuki Tominaga
  • Publication number: 20130071012
    Abstract: A image providing device provides a user with realistic and natural past-experience simulation through stereoscopic photographs. Specifically, feature-point extractors 15 and 22 extract feature points from a foreground image and a background image, respectively. A stereoscopic matching module 25 searches for pairs of feature points matching between the foreground image and the background image and obtains using the feature point pairs a transformation matrix for projecting the foreground image onto the background image. The transformation by the transformation matrix obtained by the matching unit is applied to foreground depth data, which is depth data of the foreground image. Lastly, depth based rendering is performed based on the transformed foreground depth data to obtain two or more viewpoint images corresponding to the foreground image.
    Type: Application
    Filed: February 29, 2012
    Publication date: March 21, 2013
    Applicant: PANASONIC CORPORATION
    Inventors: Germano Leichsenring, Tomoko Katayama, Hidetaka Oto, Nobuki Tominaga
  • Publication number: 20120147042
    Abstract: An electronic publication viewer (1000) includes a display target specifying unit (1100) that specifies a display target page and the position and size of the display target region, a page structure data obtaining unit (1200) that obtains page structure data corresponding to the display target page, a rendering unit (1300) that generates the display image data corresponding to the position and size of the display target region, a display image data caching unit (1400) that caches the display image data, and a display control unit (1500) that causes the display image data obtained from the rendering unit (1300) or the display image data caching unit (1400) in a position of a display unit superimposed on the display target region.
    Type: Application
    Filed: June 21, 2011
    Publication date: June 14, 2012
    Inventors: Yuki Shinomoto, Hidehiko Shin, Tomoko Katayama, Nobuki Tominaga
  • Patent number: 7168073
    Abstract: A program distribution system capable of discarding a distributed program according to the properties of the program is provided. In the program distribution system, a program is distributed from a program transmission apparatus to a program reception terminal over a network. The program transmission apparatus includes a transmission processing section. The program reception terminal includes a reception-side storage section and a discard processing section. The transmission processing section transmits a program and discarding procedure information to the program reception terminal. The discarding procedure information relates to a procedure of discarding the program performed by the program reception terminal. The reception-side storage section stores the program transmitted from the transmission processing section.
    Type: Grant
    Filed: December 9, 2002
    Date of Patent: January 23, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Takashi Asano, Nobuki Tominaga
  • Patent number: 6647547
    Abstract: A program conversion apparatus that converts a source program to an executable program, the source program including a first descriptor indicating dynamic memory allocation. The program conversion apparatus includes a specifying unit and a generating unit. The specifying unit specifies in the source program a reference descriptor that is last to be executed from reference descriptors indicating references to memory allocated by the first descriptor. The generating unit generates an instruction for freeing the allocated memory at a position in the executable program immediately following an instruction that corresponds to the specified reference descriptor.
    Type: Grant
    Filed: May 16, 2000
    Date of Patent: November 11, 2003
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Tomokazu Kanamaru, Nobuki Tominaga, Shusuke Haruna
  • Publication number: 20030134623
    Abstract: In a mobile communication system, a distributing station 1 at least transmits identification information concerning a program which the distributing station is capable of transmitting to a mobile communication terminal device having entered a service area. After generating and transmitting a distribution request for the program corresponding to the received program identification information to the distributing station 1, the mobile communication terminal device 3 stores the program which is transmitted from the distributing station 1 in a memory. Furthermore, the mobile communication terminal device 3 generates an execution instruction for the program in the memory, and transmits it to an internal interpreter. In response to the received execution instruction, the interpreter executes the program in the memory. Thus, a mobile communication system which is capable of easily downloading a program can be provided.
    Type: Application
    Filed: January 16, 2003
    Publication date: July 17, 2003
    Inventors: Tomokazu Kanamaru, Nobuki Tominaga
  • Publication number: 20030131046
    Abstract: A program distribution system capable of discarding a distributed program according to the properties of the program is provided. In the program distribution system, a program is distributed from a program transmission apparatus 1 to a program reception terminal 3 over a network 2. The program transmission apparatus 1 includes a transmission processing section 11. The program reception terminal 3 includes a reception-side storage section 34 and a discard processing section 32. The transmission processing section 11 transmits a program and discarding procedure information to the program reception terminal 3. The discarding procedure information relates to a procedure of discarding the program performed by the program reception terminal 3. The reception-side storage section 34 stores the program transmitted from the transmission processing section 11.
    Type: Application
    Filed: December 9, 2002
    Publication date: July 10, 2003
    Inventors: Takashi Asano, Nobuki Tominaga
  • Patent number: 6539433
    Abstract: Java bytecode for having home appliances perform a cooperative operation is developed by a development computer and is sent via a communications satellite from the development computer to a TV tuner&home server provided in a home. After the TV tuner&home server receives the Java bytecode, a bytecode converting unit of the TV tuner&home server determines which home appliance is the target appliance of the Java bytecode and converts the Java bytecode into native code for the microprocessor provided in the target appliance. The native code is downloaded into the target appliance via a home appliance network and the target appliance executes the downloaded native code.
    Type: Grant
    Filed: September 29, 1999
    Date of Patent: March 25, 2003
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Nobuki Tominaga, Shusuke Haruna
  • Patent number: 6438745
    Abstract: A program conversion apparatus includes: a library call instruction detecting unit for detecting each library call instruction included in an inputted object program, the library call instruction calling a source library that is an external program module; a library correspondence table that gives various information, such as correspondence between arguments of source libraries and arguments of target libraries that have the same feature as the source libraries and are called by an outputted object program; a library call instruction generating unit for converting the detected library call instruction into an instruction that calls a target library corresponding to the source library and converting instructions for setting the arguments of the source library into instructions for setting arguments of the target library by referring to the library correspondence table.
    Type: Grant
    Filed: October 18, 1999
    Date of Patent: August 20, 2002
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Tomokazu Kanamaru, Nobuki Tominaga
  • Patent number: 6425124
    Abstract: The present invention discloses a resource allocation device comprising a pattern generation unit for generating every pattern of a live variable placing within a program portion subjected to resource allocation and a resource to which the live variable is allocated; an instruction extraction unit for extracting from an instruction storage an instruction sequence corresponding to a combination of an operation placing within the program portion and the resource to which a variable in the operation is allocated, and generating a program comprising the extracted instruction sequences; a cost table for memorizing each instruction sequence and cost thereof which represents the number of execution clocks taken in execution of the instruction sequence; a cost detection unit for detecting the cost of each instruction sequence included in the program from the cost table; a total cost detection unit for summing the cost of each instruction sequence detected by the cost detection unit for each pattern generated by the p
    Type: Grant
    Filed: November 8, 1993
    Date of Patent: July 23, 2002
    Assignee: Matsushita Electric Industrial Co. Ltd.
    Inventors: Nobuki Tominaga, Akira Tanaka, Seiichi Urushibara
  • Publication number: 20010001328
    Abstract: A method number deciding unit 143 sets method numbers for methods in each class into the base method number table so that each method number within one class is different. A method table generating unit 144 generates a method table for each method, the method table including a pointer that is an offset form a first position of an executable program to an area where information relating to the method is stored, and additionally writes the generated method table at the first position of the class file. A method call instruction converting unit 145 replaces, when an instruction “invokevirtual” exists in a class file, a constant pool entry number written in an operand of the instruction with a method number, and deletes a constant pool entry indicated by the constant pool entry number.
    Type: Application
    Filed: December 26, 2000
    Publication date: May 17, 2001
    Inventors: Chikara Yoshida, Nobuki Tominaga, Shusuke Haruna
  • Patent number: 6170998
    Abstract: A processor detects a function which includes no function call instruction and no update of the return address /calculation register from an assembler program. After the detection, the processor outputs a special return address to the end of the function detected, and executes the assembler program. The processor stores a return address not only on the stack but in the return address/calculation register. When the special return instruction has been fetched, the return address is moved from the return address/calculation register without accessing to the stack.
    Type: Grant
    Filed: January 22, 1996
    Date of Patent: January 9, 2001
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kazushi Yamamoto, Shuichi Takayama, Nobuo Higaki, Nobuki Tominaga, Shinya Miyaji
  • Patent number: 5978905
    Abstract: A program translating apparatus is composed of a translation unit 103 and a link unit 108. The translation unit 103 includes a determination unit 105 which detects the stack size to be needed for each subroutine included in a source program to be translated into a machine instruction sequence and the name of a register to be retrieved in the process of each subroutine. The determination unit 105 then stores the stack size and the name detected into a file together with the machine instruction sequence. The link unit 108 includes the following units: A branch instruction detection unit 109 detects a branch instruction from the machine instruction sequence when machine instruction sequences stored in different files are linked each other. A file detection unit 110 and an acquisition unit 111 retrieve the stack size and the register name from the file which has the branch target subroutine.
    Type: Grant
    Filed: November 18, 1997
    Date of Patent: November 2, 1999
    Assignee: Matsushita Electric Industrial Co. Ltd.
    Inventors: Shuichi Takayama, Nobuo Higaki, Nobuki Tominaga, Shinya Miyaji, Seiichi Urushibara
  • Patent number: 5907694
    Abstract: The present data processing apparatus effects the pipeline operation for each of the machine cycle time with a plurality of pipeline stages processed in parallel. With respect to a load & extension instruction for instructing with the single instruction a first processing portion for reading the data shorter than the register length from RAM 19 and a second processing portion for zero-extending or the sign-extending the data into the register length, a zero-extension or a sign-extension operation in the second processing operation is executed, in a pipeline stream different from the pipeline stream where a first processing operation is executed or in a pipeline stage different from the pipeline stage where the reading from the storage portion of the first processing operation is executed.
    Type: Grant
    Filed: March 27, 1997
    Date of Patent: May 25, 1999
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masato Suzuki, Nobuo Higaki, Shinya Miyaji, Nobuki Tominaga, Yoshito Nishimichi
  • Patent number: 5850551
    Abstract: A compiler comprises a loop detecting unit for extracting information of loops, and a high-speed loop applying unit generating a first loop exclusive instruction, placing the instruction immediately before the entry of a loop, generating second loop exclusive instructions, and placing the instruction at each place to branch to the entry of the loop.
    Type: Grant
    Filed: January 22, 1996
    Date of Patent: December 15, 1998
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Shuichi Takayama, Nobuo Higaki, Nobuki Tominaga, Shinya Miyaji
  • Patent number: 5796970
    Abstract: An information processing apparatus for executing a program, the apparatus including: a register set made up of a plurality of registers; a decoding unit for decoding machine language instructions in the program and extracting a selected instruction which indicates data transfer between a plurality of registers designated by a first operand, which is made up of a single field of at least one bit which shows whether an individual register out of the register set is designated and a group field which shows whether a plurality of other registers out of the register set are designated as a group, and consecutive addresses of memory designated by a second operand as an effective address of memory; a determining unit for determining whether each bit in the single field and group field of the first operand of the extracted machine language instruction is valid; a first generating unit for generating a register number for a register corresponding to a bit determined as being valid in the single field, a second genera
    Type: Grant
    Filed: September 20, 1996
    Date of Patent: August 18, 1998
    Assignee: Matsushita Electric Industrisl Co., Ltd.
    Inventors: Nobuo Higaki, Nobuki Tominaga, Shinya Miyaji, Shuichi Takayama
  • Patent number: 5758162
    Abstract: A program translating apparatus is composed of a translation unit 103 and a link unit 108. The translation unit 103 includes a determination unit 105 which detects the stack size to be needed for each subroutine included in a source program to be translated into a machine instruction sequence and the name of a register to be retrieved in the process of each subroutine. The determination unit 105 then stores the stack size and the name detected into a file together with the machine instruction sequence. The link unit 108 includes the following units: A branch instruction detection unit 109 detects a branch instruction from the machine instruction sequence when machine instruction sequences stored in different files are linked each other. A file detection unit 110 and an acquisition unit 111 retrieve the stack size and the register name from the file which has the branch target subroutine.
    Type: Grant
    Filed: January 22, 1996
    Date of Patent: May 26, 1998
    Assignee: Matsushita Electric Industrial Co., LTD.
    Inventors: Shuichi Takayama, Nobuo Higaki, Nobuki Tominaga, Shinya Miyaji, Seiichi Urushibara
  • Patent number: 5684994
    Abstract: A resource assignment apparatus for use with a software compiler or translator for compiling or translating a high-level source program into a machine language program, wherein the resource assignment apparatus assigns the variables in the high-level source program to system resources consisting of registers, memory, and the like. The resource assignment apparatus generates assignments consisting of the variables and their live ranges and finds the interference cost incurred when assigning these various assignments to each of the various resources, consisting of data registers, address registers, memory, and the like. The apparatus sorts the assignments into groups whereby these interference costs will be the lowest. The resource element minority assignment unit then carries out the assigning of each of these groups of sorted assignment. The various assignments with live ranges which interfere are assigned to different resource elements.
    Type: Grant
    Filed: October 19, 1994
    Date of Patent: November 4, 1997
    Assignee: Matsushita Electrice Industrial Co.
    Inventors: Akira Tanaka, Junko Irimajiri, Nobuki Tominaga