Abstract: A wireless key system and location detection method determine whether a wireless key is located inside or outside a main body. A communication device in the main body transmits a wireless signal using an inner antenna and an outer antenna outside the main body having a different directivity. A wireless key measures direction of movement of the wireless key when the wireless signal is received by one of antennas having different directivities, detects one of the antennas receiving the highest signal level of the wireless signal as a first antenna, selects one of the antennas having the same directivity as the inner antenna as a second antenna according to the measured direction of movement and detected directivity of the antenna, and decides that the wireless key is inside the main body based on the signal levels of the wireless signals received by the first and second antennas.

Abstract: A wireless key system and location detection method determine whether a wireless key is located inside or outside a main body. A communication device in the main body transmits a wireless signal using an inner antenna and an outer antenna outside the main body having a different directivity. A wireless key measures direction of movement of the wireless key when the wireless signal is received by one of antennas having different directivities, detects one of the antennas receiving the highest signal level of the wireless signal as a first antenna, selects one of the antennas having the same directivity as the inner antenna as a second antenna according to the measured direction of movement and detected directivity of the antenna, and decides that the wireless key is inside the main body based on the signal levels of the wireless signals received by the first and second antennas.

Abstract: An analog semiconductor integrated circuit has an analog circuit, a PMOS and a bias adjustment circuit. The gate of the PMOS is the output section of an open drain system, and is connected to an internal node on the output side of the analog circuit. The bias adjustment circuit is connected to the internal node, and allows adjustment of the bias current in accordance with the fuse disconnection number. The relationship between the voltage when a fixed current flows to an input terminal and the fuse disconnection number that allows the optimum bias current to flow to the output section of the analog LSI is checked by using a plurality of sample analog LSIs having different threshold voltages. The voltage is measured by causing a fixed current to flow to the input terminal of a non-sample analog LSI, and the fuse disconnection number corresponding with this voltage is obtained. Thus, the fuses in the bias adjustment circuit are disconnected.

Abstract: An analog semiconductor integrated circuit has an analog circuit, a PMOS and a bias adjustment circuit. The gate of the PMOS is the output section of an open drain system, and is connected to an internal node on the output side of the analog circuit. The bias adjustment circuit is connected to the internal node, and allows adjustment of the bias current in accordance with the fuse disconnection number. The relationship between the voltage when a fixed current flows to an input terminal and the fuse disconnection number that allows the optimum bias current to flow to the output section of the analog LSI is checked by using a plurality of sample analog LSIs having different threshold voltages. The voltage is measured by causing a fixed current to flow to the input terminal of a non-sample analog LSI, and the fuse disconnection number corresponding with this voltage is obtained. Thus, the fuses in the bias adjustment circuit are disconnected.

Abstract: A comparator is constructed to exclude an adverse effect of variation of a power source potential VDD or the like on a current output Iout. The comparator comprises a first voltage follower portion which receives an input potential Vin and outputs a potential (=Vin) following the input potential, a second voltage follower portion which receives a reference voltage Vref and outputs a potential (=Vref) following the input potential, and a current subtracting portion which outputs as a comparison result (Iout) a value achieved by subtracting the amount of current flowing due to the potential difference between the power source potential VDD of the comparator and the output potential (=Vref) of the second voltage follower portion from the amount of current flowing due to the potential difference between the power source potential VDD of the comparator and the output potential (=Vin) of the first voltage follower portion.

Abstract: A semiconductor device fabrication process includes forming a Schottky layer, a cap layer covering the surface of the Schottky layer, and a Schottky electrode of a two-level structure having a lower portion that penetrates through the cap layer and reaches the Schottky layer, and having an upper portion larger than the lower portion in cross-sectional area and that overlies the cap layer. With this construction, surface defects are unlikely to occur, so that a highly reliable semiconductor device can be fabricated.

Abstract: A semiconductor device according to the invention comprises a Schottky layer, a cap layer covering the surface of the Schottky layer, and a Schottky electrode of a two-level structure, having an under structure penetrating through the cap layer and reaching the Schottky layer, and an upper structure larger than the under structure in a cross-sectional area and overlying the cap layer. With such a construction as described, surface defect is unlikely to occur, and therefore, a highly reliable semiconductor device can be fabricated.

Abstract: A semiconductor device includes a Schottky layer, a cap layer covering the surface of the Schottky layer, and a Schottky electrode of a two-level structure. The Schottky electrode has a lower portion that penetrates through the cap layer and reaches the Schottky layer, and has an upper portion larger than the lower portion in cross-sectional area and that overlies the cap layer. With this construction, surface defects are unlikely to occur, so that a highly reliable semiconductor device can be fabricated.