Patents by Inventor Nobumi Kodama
Nobumi Kodama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7200059Abstract: A burn-in test, including first to sixth steps where voltages are applied for the same lengths of time in each step, is applied to a semiconductor memory having alternately arranged bit line pairs with twist structure where the bit lines cross each other and bit line pairs with non-twist structure where the bit lines are parallel to each other. Since lengths of time in which a stress is applied for all bit lines can be equally set, no deviation occurs in lengths of time where stress is applied between the bit lines. Characteristics of memory cells can be prevented from excessively deteriorating from the burn-in test. Further, the number of bit lines not having stress applied can be minimized in the first to sixth steps. Accordingly, the ratio of the bit lines having stress applied can be increased, which reduces the burn-in test time. Thus, test cost can be reduced.Type: GrantFiled: October 28, 2005Date of Patent: April 3, 2007Assignee: Fujitsu LimitedInventors: Shinya Fujioka, Yoshiaki Okuyama, Yasuhiro Takada, Tatsuhiro Watanabe, Nobumi Kodama
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Publication number: 20060291307Abstract: A burn-in test, including first to sixth steps where voltages are applied for the same lengths of time in each step, is applied to a semiconductor memory having alternately arranged bit line pairs with twist structure where the bit lines cross each other and bit line pairs with non-twist structure where the bit lines are parallel to each other. Since lengths of time in which a stress is applied for all bit lines can be equally set, no deviation occurs in lengths of time where stress is applied between the bit lines. Characteristics of memory cells can be prevented from excessively deteriorating from the burn-in test. Further, the number of bit lines not having stress applied can be minimized in the first to sixth steps. Accordingly, the ratio of the bit lines having stress applied can be increased, which reduces the burn-in test time. Thus, test cost can be reduced.Type: ApplicationFiled: October 28, 2005Publication date: December 28, 2006Inventors: Shinya Fujioka, Yoshiaki Okuyama, Yasuhiro Takada, Tatsuhiro Watanabe, Nobumi Kodama
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Patent number: 7107504Abstract: A test apparatus for a semiconductor device, which improves the reliability of an operational test on target devices on a wafer using BOST (Built Out Self Test) and BIST (Built In Self Test). The test apparatus includes an external test unit, the BIST circuit formed in the semiconductor device, and BOST device which is coupled between the external test unit and the semiconductor device. Pattern data for a pattern dependency test is stored in the BIST circuit and pattern data for a timing dependency test is stored in the BOST device.Type: GrantFiled: February 13, 2002Date of Patent: September 12, 2006Assignee: Fujitsu LimitedInventors: Masahiro Sato, Junji Akaza, Nobumi Kodama, Hirohisa Mizuno, Takashi Imura, Yasurou Matsuzaki
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Publication number: 20030002365Abstract: A test apparatus for a semiconductor device, which improves the reliability of an operational test on target devices on a wafer using BOST (Built Out Self Test) and BIST (Built In Self Test). The test apparatus includes an external test unit, the BIST circuit formed in the semiconductor device, and BOST device which is coupled between the external test unit and the semiconductor device. Pattern data for a pattern dependency test is stored in the BIST circuit and pattern data for a timing dependency test is stored in the BOST device.Type: ApplicationFiled: February 13, 2002Publication date: January 2, 2003Applicant: Fujitsu LimitedInventors: Masahiro Sato, Junji Akaza, Nobumi Kodama, Hirohisa Mizuno, Takashi Imura, Yasurou Matsuzaki
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Patent number: 4896302Abstract: In a semiconductor memory device, a decoder circuit is located between first and second memory cell arrays. A sequence of driver circuits in the decoder circuit is provided as driver circuits common to the first and second memory cell arrays. The output terminal of the driver circuit is connected directly with a data input/output portion for the first memory cell array and connected with another data input/output portion for the second memory cell array through wirings traversing the decoder circuit.Type: GrantFiled: November 22, 1988Date of Patent: January 23, 1990Assignee: Fujitsu LimitedInventors: Kimiaki Sato, Yoshihiro Takemae, Masao Nakano, Nobumi Kodama
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Patent number: 4807193Abstract: A one-transistor one-capacitor type semiconductor memory device having a detection circuit for detecting the electric potential of a word line, to determine an appropriate timing for driving a sense amplifier, thereby improving the speed of memory operations.Type: GrantFiled: February 25, 1987Date of Patent: February 21, 1989Assignee: Fujitsu LimitedInventors: Yoshihiro Takemae, Takeo Takematsu, Kimiaki Sato, Takashi Horii, Nobumi Kodama, Makoto Yanagisawa, Yasuhiro Takada
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Patent number: 4787067Abstract: A semiconductor dynamic memory device having an improved refreshing time is disclosed wherein the memory device provides two buffer memories exclusively for the external and refresh addresses, each of the buffer memories comprising a preamplifier and a driver stage. When the falling edge of a RAS signal is detected, all the circuits are enabled in parallel, but the operation of the driver is suppressed. As soon as a CAS before RAS detector discriminates which of the falling edges of the CAS and RAS signals becomes low earlier, it sends an address driving signal to one of the drivers, and the external address or refresh address are sent immediately. Using this technique, the prior art sequential operation of discriminating the falling edges of RAS and CAS signal, sending the refresh signal, receiving it and switching the circuit from external address to refresh address is eliminated, and is replaced by a parallel operation. Thus the set up time of the dynamic memory is reduced to 1-2 n.sec.Type: GrantFiled: July 9, 1986Date of Patent: November 22, 1988Assignee: Fujitsu LimitedInventors: Yoshihiro Takemae, Masao Nakano, Kimiaki Sato, Nobumi Kodama
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Patent number: 4771407Abstract: In a semiconductor integrated circuit having first and second power supply lines for receiving a power supply voltage, an external input terminal for receiving an input signal, and a high voltage detection circuit for detecting at the external input terminal a high voltage higher than a predetermined voltage which is higher than the power supply voltage, the high voltage detection circuit comprises an input circuit connected to the external input terminal for generating circuit for generating a reference voltage; and a differential voltage amplifier connected to receive the detection voltage and the reference voltage for amplifying the difference between the detection voltage and the reference voltage, to thereby determine whether the high voltage is applied, the input circuit comprising; a level shift element connected to the external input terminal for providing the detection voltage; an impedance element connected between the level shift element and the second power supply line; and a leak current compensaType: GrantFiled: July 29, 1987Date of Patent: September 13, 1988Assignee: Fujitsu LimitedInventors: Yoshihiro Takemae, Shigeki Nozaki, Masao Nakano, Kimiaki Sato, Hatsuo Miyahara, Nobumi Kodama, Makoto Yanagisawa, Yasuhiro Takada, Satoshi Momozono
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Patent number: 4742486Abstract: In a semiconductor integrated circuit comprising an internal circuit, a device for receiving a chip select signal from the outside, a device for receiving an input signal from the outside, and a voltage detecting circuit for detecting whether or not the potential of the input signal is higher than a reference potential; the voltage detecting circuit comprises a first device for differentially comparing the potential of the input signal with the reference potential and generating an output potential in accordance with the results of the comparison, a second device for detecting a predetermined edge of the chip select signal so as to trigger the first device, and a third device for latching the output potential of the first device to the third device when the first device is triggered by the second device, the internal circuit being switched from a first mode to a second mode, or vice versa, in accordance with the output potential of the third device.Type: GrantFiled: May 8, 1986Date of Patent: May 3, 1988Assignee: Fujitsu LimitedInventors: Yoshihiro Takemae, Shigeki Nozaki, Masao Nakano, Kimiaki Sato, Nobumi Kodama
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Patent number: 4740926Abstract: A semiconductor memory device comprises a memory cell array, a bit line charge-up circuit coupled to one of a plurality of pairs of bit lines from the memory cell array for initially charging up the one pair of bit lines to a first voltage which is lower than a power source voltage used to drive the semiconductor memory device, an active restore circuit coupled to the one pair of bit lines and a switching circuit coupled to the one pair of bit lines for disconnecting the one pair of bit lines into a first pair of bit line sections on the side of the memory cell array and a second pair of bit line sections on the side of the active restore circuit after the one pair of bit lines are initially charged up to the first voltage. The active restore circuit charges up one of the pair of bit line sections on the side of the active restore circuit to a second voltage which is higher than the first voltage depending on a datum read out from the memory cell array.Type: GrantFiled: March 24, 1986Date of Patent: April 26, 1988Assignee: Fujitsu LimitedInventors: Yoshihiro Takemae, Masao Nakano, Kimiaki Sato, Nobumi Kodama
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Patent number: 4716549Abstract: A semiconductor memory device capable of compensating for variation in a discriminating voltage of a memory cell comprising a memory cell and a gate circuit for coupling the memory cell to a bit line. The device has a precharge circuit for precharging the bit line pair to a predetermined resultant precharge voltage in a reset state. The precharge circuit precharges a bit line pair with the resultant precharge voltage obtained by adding a compensating voltage to a precharge voltage in the reset state. The compensating voltage is adapted to compensate for variation in a memory cell discriminating voltage based on variation in a memory cell voltage caused by capacitive coupling of a word line to a memory capacitor due to a parasitic capacitance of a gate circuit in the active state, and the precharge voltage is adapted to optimize the memory cell discriminating voltage when it is assumed that the parasitic capacitance is not present.Type: GrantFiled: August 29, 1986Date of Patent: December 29, 1987Assignee: Fujitsu LimitedInventors: Masao Nakano, Yoshihiro Takemae, Tomio Nakano, Shigeki Nozaki, Kimiaki Sato, Nobumi Kodama
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Patent number: 4704706Abstract: A booster circuit including a precharge capacitor (C.sub.2), a precharge driver circuit (20) having a first bootstrap circuit (C.sub.59, Q.sub.58, Q.sub.61) and precharging a voltage to the precharge capacitor in a reset mode, and an output driver circuit (19) having a switching circuit (Q.sub.21) for cutting off the output of the precharged voltage of the precharged capacitor in the reset mode and a second bootstrap circuit driving the switching circuit in an operation mode. The booster circuit further includes an additional switching circuit (Q.sub.1) for outputting a voltage to be superimposed onto the precharge voltage in the operation mode.The booster circuit may be applicable to a dynamic semiconductor memory device, for boosting a voltage of a word line at a high speed and for improving integration.Type: GrantFiled: April 11, 1986Date of Patent: November 3, 1987Assignee: Fujitsu LimitedInventors: Masao Nakano, Yoshihiro Takemae, Kimiaki Sato, Nobumi Kodama