Patents by Inventor Nobumichi Fuchigami
Nobumichi Fuchigami has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20160181380Abstract: Embodiments provided herein describe systems and methods for forming semiconductor devices. A semiconductor substrate is provided. A source region and a drain region are formed on the semiconductor substrate. A gate electrode is formed between the source region and the drain region. A contact is formed above at least one of the source region and the drain region. The contact includes an insulating layer formed above the semiconductor substrate, an interface layer formed above the insulating layer, and a metallic layer formed above the interface layer. The interface layer is operable as a barrier between a material of the insulating layer and a material of the metallic layer, reduces the electrical resistance between the material of the insulating layer and the material of the metallic layer, or a combination thereof.Type: ApplicationFiled: December 19, 2014Publication date: June 23, 2016Inventors: Amol Joshi, Sean Barstow, Paul Besser, Ashish Bodke, Guillaume Bouche, Nobumichi Fuchigami, Zhendong Hong, Shaoming Koh, Albert Sanghyup Lee, Salil Mujumdar, Abhijit Pethe, Mark Victor Raymond
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Patent number: 9252360Abstract: ALD processing techniques for forming non-volatile resistive-switching memories are described. In one embodiment, a method includes forming a first electrode on a substrate, maintaining a pedestal temperature for an atomic layer deposition (ALD) process of less than 100° Celsius, forming at least one metal oxide layer over the first electrode, wherein the forming the at least one metal oxide layer is performed using the ALD process using a purge duration of less than 20 seconds, and forming a second electrode over the at least one metal oxide layer.Type: GrantFiled: August 25, 2014Date of Patent: February 2, 2016Assignee: Intermolecular, Inc.Inventors: Nobumichi Fuchigami, Pragati Kumar, Prashant B Phatak
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Publication number: 20150170837Abstract: A hafnium oxide-aluminum oxide-hafnium oxide (HAH) based multilayer stack is used as the dielectric material in the formation of decoupling capacitors employed in microelectronic logic circuits. In some embodiments, the thickness of the aluminum oxide layer in the HAH multilayer stack varies between 0.1 nm and 1 nm. In some embodiments, the thickness of the two hafnium oxide layers varies between about 3.0 nm and 4.5 nm.Type: ApplicationFiled: December 18, 2013Publication date: June 18, 2015Applicant: Intermolecular, Inc.Inventors: Sucharita Madhukar, Nobumichi Fuchigami, Imran Hashim, Wen Wu
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Publication number: 20150146341Abstract: A thin sub-layer (<15 ?) of an impurity is formed under, over, or inside a thicker layer (˜30-100 ?) of a high-k (k>12) host material. The sub-layer may be formed by atomic layer deposition (ALD). The layer and sub-layer are annealed to form a composite dielectric layer. The host material crystallizes, but the crystalline lattice and grain boundaries are disrupted near the impurity sub-layer, impeding the migration of electrons. The impurity may be a material with a lower dielectric constant than the high-k material, added in such a small relative amount that the composite dielectric is still high-k. Metal-insulator-metal capacitors may be fabricated by forming the composite dielectric layer between two electrodes.Type: ApplicationFiled: November 27, 2013Publication date: May 28, 2015Applicants: Intermolecular Inc.Inventors: Nobumichi Fuchigami, David Paul Brunco, Karthik Ramani, Dina Triyoso
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Publication number: 20140361236Abstract: ALD processing techniques for forming non-volatile resistive-switching memories are described. In one embodiment, a method includes forming a first electrode on a substrate, maintaining a pedestal temperature for an atomic layer deposition (ALD) process of less than 100° Celsius, forming at least one metal oxide layer over the first electrode, wherein the forming the at least one metal oxide layer is performed using the ALD process using a purge duration of less than 20 seconds, and forming a second electrode over the at least one metal oxide layer.Type: ApplicationFiled: August 25, 2014Publication date: December 11, 2014Inventors: Nobumichi Fuchigami, Pragati Kumar, Prashant B. Phatak
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Patent number: 8901708Abstract: This disclosure provides (a) methods of making an oxide layer (e.g., a dielectric layer) based on yttrium and titanium, to have a high dielectric constant and low leakage characteristic and (b) related devices and structures. An oxide layer having both yttrium and titanium may be fabricated either as an amorphous oxide or as an alternating series of monolayers. In several embodiments, the oxide is characterized by a yttrium contribution to total metal that is specifically controlled. The oxide layer can be produced as the result of a reactive process, if desired, via either a PVD process or, alternatively, via an atomic layer deposition process that employs specific precursor materials to allow for a common process temperature window for both titanium and yttrium reactions.Type: GrantFiled: November 13, 2012Date of Patent: December 2, 2014Assignee: Intermolecular, Inc.Inventors: Imran Hashim, Hanhong Chen, Tony Chiang, Indranil De, Nobumichi Fuchigami, Edward Haywood, Pragati Kumar, Sandra Malhotra, Sunil Shanker
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Patent number: 8847190Abstract: ALD processing techniques for forming non-volatile resistive-switching memories are described. In one embodiment, a method includes forming a first electrode on a substrate, maintaining a pedestal temperature for an atomic layer deposition (ALD) process of less than 100° Celsius, forming at least one metal oxide layer over the first electrode, wherein the forming the at least one metal oxide layer is performed using the ALD process using a purge duration of less than 20 seconds, and forming a second electrode over the at least one metal oxide layer.Type: GrantFiled: November 27, 2013Date of Patent: September 30, 2014Assignee: Intermolecular, Inc.Inventors: Nobumichi Fuchigami, Pragati Kumar, Prashant B Phatak
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Patent number: 8836002Abstract: A method for fabricating a dynamic random access memory (DRAM) capacitor stack is disclosed wherein the stack includes a first electrode, a dielectric layer, and a second electrode. The first electrode is formed from a conductive binary metal compound and the conductive binary metal compound is annealed in a reducing atmosphere to promote the formation of a desired crystal structure. The binary metal compound may be a metal oxide. Annealing the metal oxide (i.e. molybdenum oxide) in a reducing atmosphere may result in the formation of a first electrode material (i.e. MoO2) with a rutile-phase crystal structure. This facilitates the formation of the rutile-phase crystal structure when TiO2 is used as the dielectric layer. The rutile-phase of TiO2 has a higher k value than the other possible crystal structures of TiO2 resulting in improved performance of the DRAM capacitor.Type: GrantFiled: January 10, 2013Date of Patent: September 16, 2014Assignee: Intermolecular, Inc.Inventors: Karthik Ramani, Hanhong Chen, Wim Deweerd, Nobumichi Fuchigami, Hiroyuki Ode
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Patent number: 8828821Abstract: This disclosure provides a method of fabricating a semiconductor stack and associated device such as a capacitor and DRAM cell. In particular, a bottom electrode upon which a dielectric layer is to be grown may have a ruthenium-based surface. Lattice matching of the ruthenium surface with the dielectric layer (e.g., titanium oxide, strontium titanate or barium strontium titanate) helps promote the growth of rutile-phase titanium oxide, thereby leading to higher dielectric constant and lower effective oxide thickness. The ruthenium-based material also provides a high work function material, leading to lower leakage. To mitigate nucleation delay associated with the use of ruthenium, an adherence or glue layer based in titanium may be employed. A pretreatment process may be further employed so as to increase effective capacitor plate area, and thus promote even further improvements in dielectric constant and effective oxide thickness (“EOT”).Type: GrantFiled: September 18, 2009Date of Patent: September 9, 2014Assignees: Intermolecular, Inc., Elpida Memory, Inc.Inventors: Hanhong Chen, Nobumichi Fuchigami, Imran Hashim, Pragati Kumar, Sandra Malhotra, Sunil Shanker
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Patent number: 8813325Abstract: A method for fabricating a dynamic random access memory (DRAM) capacitor stack is disclosed wherein the stack includes a first electrode, a dielectric layer, and a second electrode. The first electrode is formed from a conductive binary metal compound and the conductive binary metal compound is annealed in a reducing atmosphere to promote the formation of a desired crystal structure. The binary metal compound may be a metal oxide. Annealing the metal oxide (i.e. molybdenum oxide) in a reducing atmosphere may result in the formation of a first electrode material (i.e. MoO2) with a rutile-phase crystal structure. This facilitates the formation of the rutile-phase crystal structure when TiO2 is used as the dielectric layer. The rutile-phase of TiO2 has a higher k value than the other possible crystal structures of TiO2 resulting in improved performance of the DRAM capacitor.Type: GrantFiled: April 12, 2011Date of Patent: August 26, 2014Assignees: Intermolecular, Inc., Elpida Memory, Inc.Inventors: Karthik Ramani, Nobumichi Fuchigami, Wim Deweerd, Hanhong Chen, Hiroyuki Ode
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Patent number: 8737036Abstract: This disclosure provides (a) methods of making an oxide layer (e.g., a dielectric layer) based on titanium oxide, to suppress the formation of anatase-phase titanium oxide and (b) related devices and structures. A metal-insulator-metal (“MIM”) stack is formed using an ozone pretreatment process of a bottom electrode (or other substrate) followed by an ALD process to form a TiO2 dielectric, rooted in the use of an amide-containing precursor. Following the ALD process, an oxidizing anneal process is applied in a manner is hot enough to heal defects in the TiO2 dielectric and reduce interface states between TiO2 and electrode; the anneal temperature is selected so as to not be so hot as to disrupt BEL surface roughness. Further process variants may include doping the titanium oxide, pedestal heating during the ALD process to 275-300 degrees Celsius, use of platinum or ruthenium for the BEL, and plural reagent pulses of ozone for each ALD process cycle.Type: GrantFiled: October 22, 2012Date of Patent: May 27, 2014Assignee: Intermolecular, Inc.Inventors: Hanhong Chen, Nobumichi Fuchigami, Imran Hashim, Edward L. Haywood, Pragati Kumar, Sandra G. Malhotra, Monica Sawkar Mathur, Prashant B. Phatak, Sunil Shanker
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Publication number: 20140084236Abstract: ALD processing techniques for forming non-volatile resistive-switching memories are described. In one embodiment, a method includes forming a first electrode on a substrate, maintaining a pedestal temperature for an atomic layer deposition (ALD) process of less than 100° Celsius, forming at least one metal oxide layer over the first electrode, wherein the forming the at least one metal oxide layer is performed using the ALD process using a purge duration of less than 20 seconds, and forming a second electrode over the at least one metal oxide layer.Type: ApplicationFiled: November 27, 2013Publication date: March 27, 2014Applicant: Intermolecular Inc.Inventors: Nobumichi Fuchigami, Pragati KUMAR, Prashant B. Phatak
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Patent number: 8623671Abstract: ALD processing techniques for forming non-volatile resistive-switching memories are described. In one embodiment, a method includes forming a first electrode on a substrate, maintaining a pedestal temperature for an atomic layer deposition (ALD) process of less than 100° Celsius, forming at least one metal oxide layer over the first electrode, wherein the forming the at least one metal oxide layer is performed using the ALD process using a purge duration of less than 20 seconds, and forming a second electrode over the at least one metal oxide layer.Type: GrantFiled: June 6, 2013Date of Patent: January 7, 2014Assignee: Intermolecular, Inc.Inventors: Nobumichi Fuchigami, Pragati Kumar, Prashant Phatak
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Publication number: 20130273707Abstract: ALD processing techniques for forming non-volatile resistive-switching memories are described. In one embodiment, a method includes forming a first electrode on a substrate, maintaining a pedestal temperature for an atomic layer deposition (ALD) process of less than 100° Celsius, forming at least one metal oxide layer over the first electrode, wherein the forming the at least one metal oxide layer is performed using the ALD process using a purge duration of less than 20 seconds, and forming a second electrode over the at least one metal oxide layer.Type: ApplicationFiled: June 6, 2013Publication date: October 17, 2013Inventors: Nobumichi Fuchigami, Pragati KUMAR, Prashant B. Phatak
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Publication number: 20120262835Abstract: A method for fabricating a dynamic random access memory (DRAM) capacitor stack is disclosed wherein the stack includes a first electrode, a dielectric layer, and a second electrode. The first electrode is formed from a conductive binary metal compound and the conductive binary metal compound is annealed in a reducing atmosphere to promote the formation of a desired crystal structure. The binary metal compound may be a metal oxide. Annealing the metal oxide (i.e. molybdenum oxide) in a reducing atmosphere may result in the formation of a first electrode material (i.e. MoO2) with a rutile-phase crystal structure. This facilitates the formation of the rutile-phase crystal structure when TiO2 is used as the dielectric layer. The rutile-phase of TiO2 has a higher k value than the other possible crystal structures of TiO2 resulting in improved performance of the DRAM capacitor.Type: ApplicationFiled: April 12, 2011Publication date: October 18, 2012Applicant: INTERMOLECULAR, INC.Inventors: Karthik Ramani, Nobumichi Fuchigami, Wim Deweerd, Hanhong Chen, Hiroyuki Ode
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Publication number: 20120171839Abstract: This disclosure provides a method of fabricating a semiconductor stack and associated device such as a capacitor and DRAM cell. In particular, a bottom electrode upon which a dielectric layer is to be grown may have a ruthenium-based surface. Lattice matching of the ruthenium surface with the dielectric layer (e.g., titanium oxide, strontium titanate or barium strontium titanate) helps promote the growth of rutile-phase titanium oxide, thereby leading to higher dielectric constant and lower effective oxide thickness. The ruthenium-based material also provides a high work function material, leading to lower leakage. To mitigate nucleation delay associated with the use of ruthenium, an adherence or glue layer based in titanium may be employed. A pretreatment process may be further employed so as to increase effective capacitor plate area, and thus promote even further improvements in dielectric constant and effective oxide thickness (“EOT”).Type: ApplicationFiled: September 18, 2009Publication date: July 5, 2012Applicant: INTERMOLECULAR INC.Inventors: Hanhong Chen, Nobumichi Fuchigami, Imran Hashim, Pragati Kumar, Sandra Malhotra, Sunil Shanker