Patents by Inventor Nobumitsu Fujii

Nobumitsu Fujii has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8154133
    Abstract: A low dielectric constant film/wiring line stack structure made up of a stack of low dielectric constant films and wiring lines is provided in a region on the upper surface of the semiconductor substrate except for the peripheral part of this surface. The peripheral side surface of the low dielectric constant film/wiring line stack structure is covered with a sealing film. This provides a structure in which the low dielectric constant films do not easily come off. In this case, a lower protective film is provided on the lower surface of a silicon substrate to protect this lower surface against cracks.
    Type: Grant
    Filed: March 27, 2009
    Date of Patent: April 10, 2012
    Assignee: Casio Computer Co., Ltd.
    Inventors: Taisuke Koroku, Takeshi Wakabayashi, Osamu Okada, Osamu Kuwabara, Junji Shiota, Nobumitsu Fujii
  • Patent number: 7863750
    Abstract: In this manufacturing method of a semiconductor device, after a sealing film is applied over an entire surface of a semiconductor wafer and hardened, a second groove for forming a side-section protective film is formed in the sealing film and on the top surface side of the semiconductor wafer. In other words, the sealing film is formed in a state where a groove that causes strength reduction has not been formed on the top surface side of the semiconductor wafer. Since the second groove is formed on the top surface side of the semiconductor wafer after the sealing film is formed, the semiconductor wafer is less likely to warp when the sealing film, made of liquid resin, is hardened.
    Type: Grant
    Filed: July 22, 2009
    Date of Patent: January 4, 2011
    Assignee: Casio Computer Co., Ltd.
    Inventors: Junji Shiota, Taisuke Koroku, Nobumitsu Fujii, Osamu Kuwabara, Osamu Okada
  • Publication number: 20100144096
    Abstract: First, a trench is formed in parts of a semiconductor wafer, a sealing film and other elements corresponding to a dicing street and both sides thereof. In this state, the semiconductor wafer is separated into silicon substrates by the formation of the trench. Then, a resin protective film is formed on the bottom surface of each silicon substrate including the inner part of the trench. In this case, the semiconductor wafer is separated into the silicon substrates. However, a support plate is affixed to the upper surfaces of the columnar electrode and the sealing film via an adhesive layer. Therefore, when the resin protective film is formed, it is possible to prevent the entire workpiece including the separated silicon substrates from being easily warped.
    Type: Application
    Filed: December 7, 2009
    Publication date: June 10, 2010
    Applicants: Casio Computer Co., Ltd.
    Inventors: Taisuke Koroku, Osamu Okada, Osamu Kuwabara, Junji Shiota, Nobumitsu Fujii
  • Publication number: 20100144097
    Abstract: First, a trench is formed in parts of a semiconductor wafer, a sealing film and other elements corresponding to a dicing street and both sides thereof. In this state, the semiconductor wafer is separated into silicon substrates by the formation of the trench. Then, a resin protective film is formed on the bottom surface of each silicon substrate including the inner part of the trench. In this case, the semiconductor wafer is separated into the silicon substrates. However, a support plate is affixed to the upper surfaces of the columnar electrode and the sealing film via an adhesive layer. Therefore, when the resin protective film is formed, it is possible to prevent the entire workpiece including the separated silicon substrates from being easily warped.
    Type: Application
    Filed: December 7, 2009
    Publication date: June 10, 2010
    Applicants: CASIO COMPUTER CO., LTD.
    Inventors: TAISUKE KOROKU, OSAMU OKADA, OSAMU KUWABARA, JUNJI SHIOTA, NOBUMITSU FUJII
  • Publication number: 20100144095
    Abstract: First, a trench formed in parts of a semiconductor wafer, a sealing film and others corresponding to a dicing street and both sides thereof. In this state, the semiconductor wafer is separated into silicon substrates by the formation of the trench. Then, a resin protective film is formed on the bottom surface of each silicon substrate including the inner part of the trench. In this case, the semiconductor wafer is separated into the silicon substrates. However, a support plate is affixed to the upper surfaces of the columnar electrode and the sealing film via an adhesive layer. Therefore, when the resin protective film is formed, it is possible to prevent the entirety including the separated silicon substrates from being easily warped.
    Type: Application
    Filed: December 7, 2009
    Publication date: June 10, 2010
    Applicant: Casio Computer Co., Ltd.
    Inventors: Taisuke KOROKU, Osamu Okada, Osamu Kuwabara, Junji Shiota, Nobumitsu Fujii
  • Publication number: 20100019371
    Abstract: In this manufacturing method of a semiconductor device, after a sealing film is applied over an entire surface of a semiconductor wafer and hardened, a second groove for forming a side-section protective film is formed in the sealing film and on the top surface side of the semiconductor wafer. In other words, the sealing film is formed in a state where a groove that causes strength reduction has not been formed on the top surface side of the semiconductor wafer. Since the second groove is formed on the top surface side of the semiconductor wafer after the sealing film is formed, the semiconductor wafer is less likely to warp when the sealing film, made of liquid resin, is hardened.
    Type: Application
    Filed: July 22, 2009
    Publication date: January 28, 2010
    Applicant: Casio Computer Co., Ltd.
    Inventors: Junji SHIOTA, Talsuke Koroku, Nobumitsu Fujii, Osamu Kuwabara, Osamu Okada
  • Publication number: 20090243097
    Abstract: A low dielectric constant film/wiring line stack structure made up of a stack of low dielectric constant films and wiring lines is provided in a region on the upper surface of the semiconductor substrate except for the peripheral part of this surface. The peripheral side surface of the low dielectric constant film/wiring line stack structure is covered with a sealing film. This provides a structure in which the low dielectric constant films do not easily come off. In this case, a lower protective film is provided on the lower surface of a silicon substrate to protect this lower surface against cracks.
    Type: Application
    Filed: March 27, 2009
    Publication date: October 1, 2009
    Applicant: Casio Computer Co., Ltd.
    Inventors: Taisuke KOROKU, Takeshi Wakabayashi, Osamu Okada, Osamu Kuwabara, Junji Shiota, Nobumitsu Fujii