Abstract: A semiconductor storage device includes a level shift unit that shifts level of potential of bit line pair BL, BLB when a sense amplifier starts to read potential of the bit lines. The level shift unit includes level shifting capacitors and a timing generator. Each of level shifting capacitors have one electrode connected to each bit line and form one pair by two level shifting capacitors for each bit line pair. The timing generator is connected to each of the other electrodes of the level shifting capacitors in common, and supplies a shift capacitor drive signal to a common node of the other electrodes, so as to change stored electricity amount of the level shifting capacitors at a predetermined timing.

Abstract: Provided is an intermediate potential generation circuit with a lower power supply potential. The intermediate potential generation circuit includes: a current mirror circuit including a first transistor and a second transistor each having a source input with a power supply potential; a current source circuit including a third transistor having a drain connected to a drain of the first transistor; a grounded source amplifier circuit including a fourth transistor having a gate input with the intermediate potential, and a drain connected to a drain of the second transistor; a parallel connection circuit including a fifth transistor connected in parallel with the first transistor, and a sixth transistor connected in parallel with the second transistor; and a source follower circuit including a seventh transistor and an eighth transistor having gates that are connected in common to each other, and connected with the drains of the second transistor and the sixth transistor.

Abstract: A dynamic type semiconductor memory device includes a sense amplifier connected with a bit line pair to amplify and sense a voltage difference on the bit line pair; a precharge circuit configured to precharge the bit line pair to a power supply voltage on a lower side in response to a first control signal; a memory cell capacitance having one end which is connected with the bit line pair through a first switch circuit which is controlled in response to a signal on a word line; and a reference cell capacitance having one end which is connected with the bit line pair through a second switch circuit which is controlled in response to a signal on a reference word line. The other end of the memory cell capacitance and the other end of the reference cell capacitance are electrically separated.

Abstract: A semiconductor storage device includes a level shift unit that shifts level of potential of bit line pair BL, BLB when a sense amplifier starts to read potential of the bit lines. The level shift unit includes level shifting capacitors and a timing generator. Each of level shifting capacitors have one electrode connected to each bit line and form one pair by two level shifting capacitors for each bit line pair. The timing generator is connected to each of the other electrodes of the level shifting capacitors in common, and supplies a shift capacitor drive signal to a common node of the other electrodes, so as to change stored electricity amount of the level shifting capacitors at a predetermined timing.

Abstract: Provided is an intermediate potential generation circuit with a lower power supply potential. The intermediate potential generation circuit includes: a current mirror circuit including a first transistor and a second transistor each having a source input with a power supply potential; a current source circuit including a third transistor having a drain connected to a drain of the first transistor; a grounded source amplifier circuit including a fourth transistor having a gate input with the intermediate potential, and a drain connected to a drain of the second transistor; a parallel connection circuit including a fifth transistor connected in parallel with the first transistor, and a sixth transistor connected in parallel with the second transistor; and a source follower circuit including a seventh transistor and an eighth transistor having gates that are connected in common to each other, and connected with the drains of the second transistor and the sixth transistor.

Abstract: A dynamic type semiconductor memory device includes a sense amplifier connected with a bit line pair to amplify and sense a voltage difference on the bit line pair; a precharge circuit configured to precharge the bit line pair to a power supply voltage on a lower side in response to a first control signal; a memory cell capacitance having one end which is connected with the bit line pair through a first switch circuit which is controlled in response to a signal on a word line; and a reference cell capacitance having one end which is connected with the bit line pair through a second switch circuit which is controlled in response to a signal on a reference word line. The other end of the memory cell capacitance and the other end of the reference cell capacitance are electrically separated.

Abstract: A voltage step-down circuit (100) that may provide an internal voltage (VINT) by reducing an external power source (VDD) has been disclosed. A voltage step-down circuit (100) may include a voltage step-down portion (10) and a compensation current source portion (20). Voltage step-down portion (10) may compare a reference voltage (VREF) with an internal voltage (VINT) and control an output current (I0) accordingly. An internal circuit (1) connected to receive internal voltage (VINT) may transition from a standby state to an active state in accordance with an activation signal. Compensation current source portion (20) may provide a compensation current (Ic) when internal circuit (1) is in a standby state. In this way, voltage step-down portion (10) may be biased to provide sufficient output current (I0) so that a response time may be improved and variations in internal voltage (VINT) may be reduced.

Abstract: A voltage step-down circuit (100) that may provide an internal voltage (VINT) by reducing an external power source (VDD) has been disclosed. A voltage step-down circuit (100) may include a voltage step-down portion (10) and a compensation current source portion (20). Voltage step-down portion (10) may compare a reference voltage (VREF) with an internal voltage (VINT) and control an output current (I0) accordingly. An internal circuit (1) connected to receive internal voltage (VINT) may transition from a standby state to an active state in accordance with an activation signal. Compensation current source portion (20) may provide a compensation current (Ic) when internal circuit (1) is in a standby state. In this way, voltage step-down portion (10) may be biased to provide sufficient output current (I0) so that a response time may be improved and variations in internal voltage (VINT) may be reduced.

Abstract: Decholesterolized and defatted egg powder is obtained by removing at least 95% of the cholesterol and neutral fat and retaining 30% or more of the phospholipids, based on the content thereof in the whole egg or yolk. Said powder is obtained by removing moisture from whole egg or yolk and extracting cholesterol and neutral fat from the dried whole egg or yolk with liquid dimethylether.

Abstract: A process for obtaining yolk lecithin from a raw egg yolk which comprises subjecting a raw egg yolk to extraction with liquid dimethyl ether to obtain an extract and dehydrating the extract to an extent that the water content is not more than 20% by weight, whereby a lecithin-rich fraction is obtained as a separate phase from a neutral lipids-fraction. The isolated lecithin-rich fraction may further be subjected to a second-stage dehydration to give a product in which the lecithin content is as high as 50 to 85% by weight and the water content is very small, for example, below 2 to nearly 0% by weight. By the process of the present invention, there can be obtained a high quality lecithin in high yield.

Abstract: Hydrophilic and lipophilic flavor and odor producing components of natural products are obtained by extraction with defined dimethyl either-water mixtures.

Abstract: Hydrophilic and lipophilic flavor and odor producing components of natural products are obtained by extraction with defined dimethyl either-water mixtures.

Abstract: A method for the removal of Aflatoxin from materials including cereals, oil seeds and feedstuffs contaminated therewith comprising contacting said materials with a mixed solvent system of liquid dimethyl ether and water. The water is employed in an amount of 2 to 8 % by weight with respect to the liquid dimethyl ether. Such method which can reduce the Aflatoxin content to 15 ppb or less, can be conducted at low temperatures so that no proteins contained therein are denaturated. Further, the spent solvent system containing Aflatoxin can be easily regenerated by contacting it with activated carbon and recycled.

Abstract: Method for the regeneration of an activated carbon having adsorbates adsorbed therein characterized by removing the adsorbates by liquid dimethyl ether or a mixture of liquid dimethyl ether and water. By such method, the spent carbon can be effectively regenerated without degrading the absorption capacity and mechanical strength thereof. Further, valuable substances in the desorbed adsorbates can be effectively concentrated and recovered by a simple additional operation.