Patents by Inventor Nobuo Hashizume

Nobuo Hashizume has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5298485
    Abstract: A logic circuit device includes a superconductive body formed of a ceramic superconductive material. The ceramic superconductive material has random grain boundaries which act as weak couplings. The ceramic superconductive material also has a magneto-resistive property. There is at least one conductor arranged near the ceramic superconductive body in order to exert a magnetic field on the ceramic superconductive body. The ceramic superconductive body changes its resistance in response to the magnetic field generated by the conductor. The ceramic superconductive body can be used as part of a logic circuit.
    Type: Grant
    Filed: November 30, 1992
    Date of Patent: March 29, 1994
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Shoei Kataoka, Hiroya Sato, Shuhei Tsuchimoto, Hideo Nojima, Shinji Toyoyama, Masayoshi Koba, Nobuo Hashizume, Eizo Ohno, Susumu Saitoh
  • Patent number: 5126668
    Abstract: An apparatus for magnetic measurement using superconductive magneto-resistive film which is disposed in a magnetic field with the surface of the superconductive magneto-resistive film directed in parallel with the direction of the magnetic field so that the magnetic hysterisis property of the film can be avoided and the accuracy of the measurement can be much improved.
    Type: Grant
    Filed: July 14, 1989
    Date of Patent: June 30, 1992
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Hideo Nojima, Shoei Kataoka, Shuhei Tsuchimoto, Nobuo Hashizume
  • Patent number: 5055785
    Abstract: A ceramic superconductive magneto-resistive element which has weak grain boundaries is highly sensitive to weak magnetic fields. The magnetic field is measured by the use of an electronic circuit. A comparator is used for comparing an output and reference voltage of the element. When there is a difference between the output and reference voltage bias current is used to equalize these voltages.
    Type: Grant
    Filed: July 3, 1989
    Date of Patent: October 8, 1991
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Hidetaka Shintaku, Shuhei Tsuchimoto, Nobuo Hashizume, Shoei Kataoka
  • Patent number: 5048336
    Abstract: A moisture-sensitive device comprising a substrate such as silicon substrate, a pair of belt-like heating elements extending over recesses formed in the substrate, the heating elements being composed of a resistive film of platinum or nickel and a heat-resistant insulating film covering the resistive film in which one of the heating elements acts as a detector element and the other as a reference element, which device can exactly determine an absolute humidity irrespective of sudden changes of temperature.
    Type: Grant
    Filed: December 29, 1989
    Date of Patent: September 17, 1991
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Takashi Sugihara, Kazutaka Uda, Hiroki Tabuchi, Shuji Miyoshi, Yasuhiko Inami, Nobuo Hashizume, Hisatoshi Furubayashi
  • Patent number: 5041880
    Abstract: A logic device includes a ceramic superconducting element having magneto-resistive characteristics, and three electrodes provided adjacent the ceramic superconducting element, and constructed in such a manner that a current is applied to one of the three electrode so that a magnetic field greater than a threshold magnetic field is normally applied to the ceramic superconducting element, and the other electrodes are used for increasing and decreasing the magnetic field. A memory device includes a superconducting loop at least one portion thereof being formed by a ceramic superconducting element having grain boundaries, and an electrode provided in approximation to said ceramic superconducting element, whereby a current flowing through a portion of said superconducting loop which is other than said ceramic superconducting element can be captured in said superconducting loop by a control of a magnetic field generated by the current flowing through said electrode.
    Type: Grant
    Filed: June 14, 1989
    Date of Patent: August 20, 1991
    Assignees: Sharp Kabushiki Kaisha, Michitada Morisue
    Inventors: Hideo Nojima, Shoei Katoaka, Nobuo Hashizume, Shuhei Tsuchimoto, Michitada Morisue
  • Patent number: 4811070
    Abstract: A semiconductor device comprises a first semiconductor region having formed thereon a second semiconductor region which forms at its one surface an energy barrier with respect to minority carriers of the first semiconductor region, a conductive region in contact with the other surface of the second semiconductor region, and an induced layer formed in the operating state in a surface portion of the first semiconductor region in contact with the second semiconductor region under the conductive region, the carriers being transported across the induced layer to the first semiconductor region, whereby the conductive region acts as an emitter, the induced layer acts as a base and the first semiconductor layer acts as a collector of a transistor.
    Type: Grant
    Filed: March 27, 1987
    Date of Patent: March 7, 1989
    Assignees: Agency of Industrial Science & Technology, Ministry of Internationl Trade & Industry
    Inventors: Yutaka Hayashi, Kazuhiko Matsumoto, Nobuo Hashizume
  • Patent number: 4107718
    Abstract: A semiconductor device including a cathode and an anode for applying a bias electric field to a semiconductor exhibiting negative conductivity under high electric field, a region in which the electric field is locally lower than that in other regions, at least two signal electrodes of field effect type additionally provided in the region of said lower field to which signals are supplied to control the generation of high electric field domains for the performance of logical operations.
    Type: Grant
    Filed: April 5, 1977
    Date of Patent: August 15, 1978
    Assignee: Agency of Industrial Science & Technology
    Inventors: Shoei Kataoka, Nobuo Hashizume, Hiroshi Kodera
  • Patent number: 4090155
    Abstract: A transmission line is disclosed which comprises a conductive layer, a resistive semiconductor layer disposed on the conductive layer and a blocking electrode disposed on the resistive semiconductor layer. By applying a biasing voltage between the blocking electrode and the conductive layer, a depletion layer is produced in the resistive semiconductor layer, the depletion layer formed in the semiconductor layer being used as a medium for transmission of electromagnetic wave.
    Type: Grant
    Filed: March 22, 1976
    Date of Patent: May 16, 1978
    Assignee: Agency of Industrial Science & Technology
    Inventors: Hiroshi Tateno, Shoei Kataoka, Nobuo Hashizume, Yasuo Komamiya
  • Patent number: 4047199
    Abstract: The invention disclosed relates to a bulk semiconductor device having a semiconductor element exhibiting a negative conductivity under a high electric field and being capable of generating a high electric field domain therein. The semiconductor device includes two ohmic electrodes disposed at opposite ends to apply a bias voltage, at least one means for generating a high electric field domain in the semiconductor device by means applying an input signal to the generating means, at least one means for inhibiting generation of a high electric field domain by means applying another input signal to the inhibiting means, and means for detecting the existence of the high electric field domain in the semiconductor device to produce an output signal.
    Type: Grant
    Filed: October 1, 1975
    Date of Patent: September 6, 1977
    Assignee: Agency of Industrial Science & Technology
    Inventors: Shoei Kataoka, Yasuo Komaniya, Nobuo Hashizume, Kazutaka Tomizawa, Mitsuo Kawashima
  • Patent number: 4021680
    Abstract: Disclosed is a bulk semiconductor device which employs a semiconductor element exhibiting negative conductivity under a high electric field. Said semiconductor element has at least two regions and at least one bridge portion and each region thereof is connected with the region adjacent thereto by a bridge portion. Means for controlling the lateral spatial growth of a high electric field domain is provided on or near each bridge portion. The growth of a high electric field domain generated in one of the regions into the adjacent region is controlled by applying a signal to said controlling means.
    Type: Grant
    Filed: October 1, 1975
    Date of Patent: May 3, 1977
    Assignee: Agency of Industrial Science & Technology
    Inventors: Shoei Kataoka, Yasuo Komamiya, Mitsuo Kawashima, Nobuo Hashizume, Kazutaka Tomizawa