Patents by Inventor Nobuo Hironaga
Nobuo Hironaga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10242994Abstract: A monolithic three-dimensional memory device includes a first alternating stack of first insulating layers and first electrically conductive layers located over a top surface of a substrate, an insulating cap layer overlying the first alternating stack, a second alternating stack of second insulating layers and second electrically conductive layers and overlying the insulating cap layer, memory openings extending through the second alternating stack, the insulating cap layer, and the first alternating stack, memory stack structures located within the memory openings, and annular spacers located within the insulating cap layer and laterally surrounding a respective one of the memory stack structures.Type: GrantFiled: September 14, 2017Date of Patent: March 26, 2019Assignee: SANDISK TECHNOLOGIES LLCInventors: Takashi Inomata, Nobuo Hironaga, Junichi Ariyoshi, Tadashi Nakamura
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Publication number: 20180006049Abstract: A monolithic three-dimensional memory device includes a first alternating stack of first insulating layers and first electrically conductive layers located over a top surface of a substrate, an insulating cap layer overlying the first alternating stack, a second alternating stack of second insulating layers and second electrically conductive layers and overlying the insulating cap layer, memory openings extending through the second alternating stack, the insulating cap layer, and the first alternating stack, memory stack structures located within the memory openings, and annular spacers located within the insulating cap layer and laterally surrounding a respective one of the memory stack structures.Type: ApplicationFiled: September 14, 2017Publication date: January 4, 2018Inventors: Takashi INOMATA, Nobuo HIRONAGA, Junichi ARIYOSHI, Tadashi NAKAMURA
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Patent number: 9502429Abstract: A trench can be formed through a stack of alternating plurality of first material layers and second material layers. A dielectric material liner and a trench fill material portion can be formed in the trench. The dielectric material liner and portions of first material layer can be simultaneously etched to form laterally-extending cavities having level-dependent lateral extents. A set of stepped surfaces can be formed by removing unmasked portions of the second material layers. Alternately, an alternating sequence of processing steps including vertical etch processes and lateral recess processes can be employed to laterally recess second material layers and to form laterally-extending cavities having level-dependent lateral extents. Lateral cavities can be simultaneously formed in multiple levels such that levels having laterally-extending cavities of a same lateral extent are offset across multiple integrated cavities.Type: GrantFiled: November 26, 2014Date of Patent: November 22, 2016Assignee: SANDISK TECHNOLOGIES LLCInventor: Nobuo Hironaga
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Publication number: 20160148946Abstract: A trench can be formed through a stack of alternating plurality of first material layers and second material layers. A dielectric material liner and a trench fill material portion can be formed in the trench. The dielectric material liner and portions of first material layer can be simultaneously etched to form laterally-extending cavities having level-dependent lateral extents. A set of stepped surfaces can be formed by removing unmasked portions of the second material layers. Alternately, an alternating sequence of processing steps including vertical etch processes and lateral recess processes can be employed to laterally recess second material layers and to form laterally-extending cavities having level-dependent lateral extents. Lateral cavities can be simultaneously formed in multiple levels such that levels having laterally-extending cavities of a same lateral extent are offset across multiple integrated cavities.Type: ApplicationFiled: November 26, 2014Publication date: May 26, 2016Inventor: Nobuo HIRONAGA
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Patent number: 8349087Abstract: A semiconductor device manufacturing method includes loading plural dry-etched wafers one by one in a container having a side door so as to be disposed substantially horizontally and in layers vertically therein; and blowing out a purge gas horizontally to those wafers loaded in the container for 30 sec or more after all the subject wafers are loaded in the container while the side door is open.Type: GrantFiled: January 12, 2010Date of Patent: January 8, 2013Assignee: Renesas Electronics CorporationInventors: Hidetaka Nambu, Nobuo Hironaga, Futoshi Ota, Toru Yokoyama, Osamu Sugawara, Ryo Satou, Masato Tamura
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Publication number: 20100184296Abstract: A semiconductor device manufacturing method includes loading plural dry-etched wafers one by one in a container having a side door so as to be disposed substantially horizontally and in layers vertically therein; and blowing out a purge gas horizontally to those wafers loaded in the container for 30 sec or more after all the subject wafers are loaded in the container while the side door is open.Type: ApplicationFiled: January 12, 2010Publication date: July 22, 2010Applicant: NEC Electronics CorporationInventors: Hidetaka Nambu, Nobuo Hironaga, Futoshi Ota, Toru Yokoyama, Osamu Sugawara, Ryo Satou, Masato Tamura
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Patent number: 7229921Abstract: In a method of manufacturing a semiconductor device, a first wiring line composed of a copper containing metal film is formed on or above a semiconductor substrate. A first interlayer insulating film is formed on a whole surface of the semiconductor substrate to cover the first wiring line. The first interlayer insulating film is selectively removed to form a connection hole reaching the first wiring line. A barrier metal film is formed to cover an inner surface of the connection hole and then a copper containing metal film is formed to fill the connection hole. The copper containing metal film formed outside the connection hole is removed. A second interlayer insulating film is formed on a whole surface of the semiconductor substrate to cover the copper containing metal film formed in the connection hole. The second interlayer insulating film is selectively removed to form a wiring line groove such that the copper containing metal film formed in the connection hole is exposed at a bottom.Type: GrantFiled: October 28, 2002Date of Patent: June 12, 2007Assignee: NEC Electronics CorporationInventors: Nobuo Hironaga, Toshiyuki Takewaki, Hiroyuki Kunishima, Yoshiaki Yamamoto
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Patent number: 6890864Abstract: There are provided a semiconductor device fabricating method for forming a wiring layer on a semiconductor substrate, followed by cleaning, which may prevent elution and oxidation of the wiring layer, and a treating liquid used in the fabricating method. A Cu wiring, an interlayer film over the Cu wiring and an opening in the interlyaer film to expose the surface of the Cu wiring are formed in a plasma atmosphere. IPA is sprayed to the semiconductor device, and then, an organic release process is performed thereto with an amine solvent to remove an etching residue. The semiconductor device is rinsed with the IPA again to remove the remaining amine, and then is cleaned with a treating liquid, which is alkalescent. Then, it is rinsed with pure water or CO2 water and is dried.Type: GrantFiled: January 10, 2003Date of Patent: May 10, 2005Assignee: NEC Electronics CorporationInventors: Hidemitsu Aoki, Kenichi Nakabeppu, Hiroaki Tomimori, Toshiyuki Takewaki, Nobuo Hironaga, Hiroyuki Kunishima
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Publication number: 20030173671Abstract: In a method of manufacturing a semiconductor device, a first wiring line composed of a copper containing metal film is formed on or above a semiconductor substrate. A first interlayer insulating film is formed on a whole surface of the semiconductor substrate to cover the first wiring line. The first interlayer insulating film is selectively removed to form a connection hole reaching the first wiring line. A barrier metal film is formed to cover an inner surface of the connection hole and then a copper containing metal film is formed to fill the connection hole. The copper containing metal film formed outside the connection hole is removed. A second interlayer insulating film is formed on a whole surface of the semiconductor substrate to cover the copper containing metal film formed in the connection hole. The second interlayer insulating film is selectively removed to form a wiring line groove such that the copper containing metal film formed in the connection hole is exposed at a bottom.Type: ApplicationFiled: October 28, 2002Publication date: September 18, 2003Applicant: NEC CORPORATIONInventors: Nobuo Hironaga, Toshiyuki Takewaki, Hiroyuki Kunishima, Yoshiaki Yamamoto
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Publication number: 20030134507Abstract: There are provided a semiconductor device fabricating method for forming a wiring layer on a semiconductor substrate, followed by cleaning, which may prevent elution and oxidation of the wiring layer, and a treating liquid used in the fabricating method. A Cu wiring, an interlayer film over the Cu wiring and an opening in the interlyaer film to expose the surface of the Cu wiring are formed in a plasma atmosphere. IPA is sprayed to the semiconductor device, and then, an organic release process is performed thereto with an amine solvent to remove an etching residue. The semiconductor device is rinsed with the IPA again to remove the remaining amine, and then is cleaned with a treating liquid, which is alkalescent. Then, it is rinsed with pure water or CO2 water and is dried.Type: ApplicationFiled: January 10, 2003Publication date: July 17, 2003Applicant: NEC CorporationInventors: Hidemitsu Aoki, Kenichi Nakabeppu, Hiroaki Tomimori, Toshiyuki Takewaki, Nobuo Hironaga, Hiroyuki Kunishima
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Publication number: 20030027418Abstract: There are provided a semiconductor device fabricating method for forming a wiring layer on a semiconductor substrate, followed by cleaning, which may prevent elution and oxidation of the wiring layer, and a treating liquid used in the fabricating method. A Cu wiring, an interlayer film over the Cu wiring and an opening in the interlyaer film to expose the surface of the Cu wiring are formed in a plasma atmosphere. IPA is sprayed to the semiconductor device, and then, an organic release process is performed thereto with an amine solvent to remove an etching residue. The semiconductor device is rinsed with the IPA again to remove the remaining amine, and then is cleaned with a treating liquid, which is alkalescent. Then, it is rinsed with pure water or CO2 water and is dried.Type: ApplicationFiled: July 10, 2002Publication date: February 6, 2003Applicant: NEC CorporationInventors: Hidemitsu Aoki, Kenichi Nakabeppu, Hiroaki Tomimori, Toshiyuki Takewaki, Nobuo Hironaga, Hiroyuki Kunishima