Abstract: The video signal transmission apparatus according to the present disclosure transmits a pixel clock, signals, and image data which all are supplied from a video signal source. The signals include a vertical synchronizing signal, a horizontal synchronizing signal, a data enable signal, and a field signal. Each of the signals and the image data are in synchronization with the pixel clock. The video signal transmission apparatus includes a first format data processor and a transmitter. The first format data processor generates a plurality of data expressing a format of an image screen, based on the pixel clock and the signals, and for outputting the plurality of the data sequentially as serial data. The transmitter transmits, to a receiver by serial transmission, the image data, the vertical synchronizing signal, the pixel clock, and the serial data obtained from the first format data processor.

Abstract: The video signal transmission apparatus according to the present disclosure transmits a pixel clock, signals, and image data which all are supplied from a video signal source. The signals include a vertical synchronizing signal, a horizontal synchronizing signal, a data enable signal, and a field signal. Each of the signals and the image data are in synchronization with the pixel clock. The video signal transmission apparatus includes a first format data processor and a transmitter. The first format data processor generates a plurality of data expressing a format of an image screen, based on the pixel clock and the signals, and for outputting the plurality of the data sequentially as serial data. The transmitter transmits, to a receiver by serial transmission, the image data, the vertical synchronizing signal, the pixel clock, and the serial data obtained from the first format data processor.

Abstract: The signal transmitting device of a signal transmitting/receiving device according to the present disclosure includes a signal processing unit that outputs a video signal as parallel data together with the first clock (the pixel clock); a first buffer memory to which the parallel data is written based on the first clock from the signal processing unit, and from which the written parallel data is read based on the second clock having a constant frequency equal to or higher than that of the first clock; and a transmitting unit. The transmitting unit receives the parallel data read from the first buffer memory and the second clock, converts the parallel data into serial data, and outputs the serial data to the signal line based on the second clock. The first buffer memory and the transmitting unit are formed of an FPGA (field-programmable gate array).

Abstract: The signal transmitting device of a signal transmitting/receiving device according to the present disclosure includes a signal processing unit that outputs a video signal as parallel data together with the first clock (the pixel clock); a first buffer memory to which the parallel data is written based on the first clock from the signal processing unit, and from which the written parallel data is read based on the second clock having a constant frequency equal to or higher than that of the first clock; and a transmitting unit. The transmitting unit receives the parallel data read from the first buffer memory and the second clock, converts the parallel data into serial data, and outputs the serial data to the signal line based on the second clock. The first buffer memory and the transmitting unit are formed of an FPGA (field-programmable gate array).