Patents by Inventor Nobuo Inami

Nobuo Inami has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6205054
    Abstract: A nonvolatile memory includes paired memory elements each including a storage transistor having a control gate and a floating gate. Through a write operation, one of the storage transistors is brought into a depletion state and the other storage transistor is brought into an enhancement state. Subsequently, a connection transistor is operated in order to serially connect the paired memory elements. As result, a binary signal corresponding to the statuses of the paired storage transistors is outputted.
    Type: Grant
    Filed: December 13, 1999
    Date of Patent: March 20, 2001
    Assignee: Global Alliance Inc.
    Inventor: Nobuo Inami
  • Patent number: 4374332
    Abstract: Within a semiconductor device having two sets of CMOS inverters, the two sets of CMOS inverters are electrically connected in series to a power source for supplying electric power to the semiconductor device. The two sets of CMOS inverters are formed in an oscillating circuit for producing a time base signal and a frequency dividing circuit, respectively. Device operating current and power consumption are accordingly reduced.
    Type: Grant
    Filed: September 16, 1980
    Date of Patent: February 15, 1983
    Assignee: Kabushiki Kaisha Daini Seikosha
    Inventors: Nobuo Inami, Kojiro Tanaka