Patents by Inventor Nobuo Itoh
Nobuo Itoh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20090245443Abstract: A diversity receiver is provided. A first adaptive array unit includes a first combiner that obtains a first combined signal comprised mainly of a first wave of received signals by combining received signals of a plurality of antennas with using first complex weights. A second adaptive array unit includes a first component subtractor that subtract the first combined signal from the respective received signals and a second combiner that obtains a second combined signal comprised mainly of a second wave of the received signals by combining the received signals and outputs of the first component subtractor with using second complex weights. The first combiner includes a delay wave suppressing unit that generates a suppressed signal in which components of the second wave is suppressed from the first combined signal and a first weight coefficient operating unit that determines the first complex weights by complex correlation operation between outputs of the delay wave suppressing unit and the received signals.Type: ApplicationFiled: March 30, 2009Publication date: October 1, 2009Applicant: FUJITSU TEN LIMITEDInventors: Kazuo TAKAYAMA, Hidenori GOHHARA, Takumi YOSHIMOTO, Katsushi SANDA, Nobuo ITOH
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Patent number: 7035348Abstract: A receiver configured to receive a plurality of signals k (k=1, 2, . . . , M) allocated in a first frequency band. The receiver includes a frequency conversion section for reallocating the signals k in a second frequency band for sampling by a single AD converter at a sampling frequency fs such that digital data of the sampled signals k are obtained in a third frequency band extending from zero Hz to a frequency represented by fs/2; and a signal extraction section for extracting a target base band signal k from the digital data obtained by the AD conversion section. The frequency conversion section performs the reallocation in such a manner that at least a frequency represented by Jfs/2 (J is an integer) is located between the frequencies of at least two of the signals k and that the sampled signals do not overlap.Type: GrantFiled: May 24, 2002Date of Patent: April 25, 2006Assignee: Kabushiki Kaisha Toyota Chuo KenkyushoInventors: Noriyoshi Suzuki, Tomohisa Harada, Tsutayuki Shibata, Hisanori Uda, Hiroaki Hayashi, Nobuo Itoh
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Patent number: 6654425Abstract: A digital modulation method in which at a head of an input block (pre-translation), each of a plurality of different types of initial data of t bits is multiplexed to generate a plurality of different types of multiplexed blocks, t bits at the head and immediately following t bits of each of the multiplexed blocks are subjected to exclusive OR operation, the immediately following t bits are replaced by the result of operation, the replaced t bits and the immediately following t bits are subjected to an exclusive OR operation, and the immediately following t bits are replaced by the result of operation, and thereafter in the similar manner, a convolution operation is executed. A plurality of different types of translated blocks are produced by the convolution operation, and DC components of thus provided translated blocks are calculated, respectively, absolute values of the respective DC components are compared with each other, and a translated block having the minimum value is selected and output externally.Type: GrantFiled: June 22, 1999Date of Patent: November 25, 2003Assignee: Sanyo Electric Co., Ltd.Inventors: Akiomi Kunisa, Nobuo Itoh, Seiichiro Takahashi
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Publication number: 20030128774Abstract: A receiver apparatus receives substantially concurrently a plurality of signals k (k=1, 2, . . . , M) that have been transmitted while being allocated in a broad, first frequency band. The receiver apparatus includes a frequency conversion section for reallocating the signals k in a second frequency band within which the signals k can be sampled by a single AD converter; an AD conversion section for sampling the signals k having being reallocated into the second frequency band at a sampling frequency fs such that digital data of the sampled signals k are obtained in a third frequency band extending from zero Hz to a frequency represented by fs/2; and a signal extraction section for extracting a target base band signal k from the digital data obtained through the sampling by the AD conversion section.Type: ApplicationFiled: May 24, 2002Publication date: July 10, 2003Applicant: KABUSHIKI KAISHA TOYOTA CHUO KENKYUSHOInventors: Noriyoshi Suzuki, Tomohisa Harada, Tsutayuki Shibata, Hisanori Uda, Hiroaki Hayashi, Nobuo Itoh
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Publication number: 20020057736Abstract: Interlace images are separated at every field by a frame/field transforming section, and wavelet transformation is performed for every field by an interfield wavelet transforming section. Specifically, a plurality of odd or even fields in time series are determined as one group, these fields are subjected to the wavelet transformation to separate at predetermined spatial frequencies. Among the plurality of images separated at predetermined spatial frequencies, a motion vector common to the groups is calculated in view of a change with time of an arbitrary image component to perform motion compensation. The images subjected to the interfield wavelet transformation are further subjected to wavelet transformation by an intrafield wavelet transforming section so to be coded. Thus, an operational volume for calculating motion vector for the image coding is reduced, and block distortion is remedied.Type: ApplicationFiled: August 26, 1998Publication date: May 16, 2002Inventors: HIDEYUKI FUJI, MAYUMI NIWA, NOBUO ITOH
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Patent number: 6324138Abstract: A meandering groove is formed in a digital disk (10) with a wobble signal that is wobbled to reproduce a clock signal. The wobble signal is read out by an optical head (26). An address detection circuit (40) detects an address signal that is multiplexed with the wobble signal. A PLL oscillation circuit (24) provides a clock signal in synchronization with the wobble signal. Data is modulated by a modulation circuit (16) according to the clock signal and a timing signal based on the address signal, and recorded on the digital disk (10). In reproduction, a RF signal in the wobble signal is converted into a digital signal by an A/D converter (42). The signal is demodulated by a demodulation circuit (44) for data output.Type: GrantFiled: June 23, 2000Date of Patent: November 27, 2001Assignee: Sanyo Electric Co., Ltd.Inventors: Yoshihiro Hori, Hisashi Matsuyama, Akiomi Kunisa, Nobuo Itoh, Seiichiro Takahashi, Toshiaki Hioki, Kenji Asano, Noboru Mamiya, Yoshiharu Uchihara, Kenji Nakao, Satoshi Sumi, Kenji Torazawa
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Patent number: 6198710Abstract: A meandering groove is formed in a digital disk (10) with a wobble signal that is wobbled to reproduce a clock signal. The wobble signal is read out by an optical head (26). An address detection circuit (40) detects an address signal that is multiplexed with the wobble signal. A PLL oscillation circuit (24) provides a clock signal in synchronization with the wobble signal. Data is modulated by a modulation circuit (16) according to the clock signal and a timing signal based on the address signal, and recorded on the digital disk (10). In reproduction, a RF signal in the wobble signal is converted into a digital signal by an A/D converter (42). The signal is demodulated by a demodulation circuit (44) for data output.Type: GrantFiled: June 9, 1998Date of Patent: March 6, 2001Assignee: Sanyo Electric Co., Ltd.Inventors: Yoshihiro Hori, Hisashi Matsuyama, Akiomi Kunisa, Nobuo Itoh, Seiichiro Takahashi, Toshiaki Hioki, Kenji Asano, Noboru Mamiya, Yoshiharu Uchihara, Kenji Nakao, Satoshi Sumi, Kenji Torazawa
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Patent number: 6141787Abstract: A digital modulator which inputs a data stream to convert to a channel bit stream. The multiplexed data block is generated by multiplexing dummy data to any position within each data block cut out of the data stream one by one. The first Reed-Solomon code is generated by Reed-Solomon-encoding the multiplexed data block as an information part. A plurality of second Reed-Solomon codes are generated by adding a plurality of Reed-Solomon codes for scrambling each of which has identification data showing its scrambling pattern in the same position as that of the dummy data, and the code length of information part and parity part is the same as the first Reed-Solomon code. The second Reed-Solomon code in which the characteristics becomes desirable after modulation among the plurality of the second Reed-Solomon codes is set for output.Type: GrantFiled: January 15, 1999Date of Patent: October 31, 2000Assignee: Sanyo Electric Co., Ltd.Inventors: Akiomi Kunisa, Nobuo Itoh
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Patent number: 6079041Abstract: A digital modulation circuit which minimizes a DC component of an NRZI modulated code sequence while setting the T.sub.max and T.sub.W not to be varied. An m-n coding mode is determined for each data block composed of the predetermined number of m-bit datawords. That is, an m-n coding mode which minimizes the absolute value of the DSV is selected and the selected m-n coding mode is utilized for the m-n coding of the current data block. The code indicating the selected m-n coding mode is multiplexed to the m-n coded current block. An m--m mapping table is also determined for each data block. That is, such an m--m mapping table that minimizes the absolute value of the DSV is selected and the selected m--m mapping table is utilized for the m--m translation of the current data block. Then, the m--m mapped data block is m-n translated into a code block composed of the same number of n-bit codewords by utilizing the single m-n translation table.Type: GrantFiled: August 2, 1996Date of Patent: June 20, 2000Assignee: Sanyo Electric Co., Ltd.Inventors: Akiomi Kunisa, Seiichiro Takahashi, Nobuo Itoh
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Patent number: 5739779Abstract: Several different types of look-up tables are available in the present invention. That is, one look-up table is selected for each m-bit dataword according to the number of consecutive 0's at lower digits, which include a lowermost digit, of the n-bit codeword preceding thereto and the encoding is performed by using the selected look-up table. Furthermore, the bit-pattern at the lower digits, which include a lowermost digit, of a current n-bit codeword is replaced according to the number of consecutive 0's at upper digits, which include an uppermost digit, of the n-bit codeword following thereafter.Type: GrantFiled: August 20, 1996Date of Patent: April 14, 1998Assignee: Sanyo Electric Co., Ltd.Inventors: Akiomi Kunisa, Seiichiro Takahashi, Nobuo Itoh
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Patent number: 5071558Abstract: A sodium bicarbonate dialysate comprising an electrolyte granule A composed mainly of sodium chloride and containing no sodium bicarbonate and an electrolyte granule B containing sodium bicarbonate, wherein the granule B is granules of sodium bicarbonate primary particles having a particle size of at most 250 .mu.m, and the particle size of the secondary particles after granulation is from 0.1 to 10 mm.Type: GrantFiled: August 8, 1990Date of Patent: December 10, 1991Assignees: Nikkiso Co., Ltd., Towa Pharmaceutical Co., Ltd.Inventor: Nobuo Itoh
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Patent number: 4898837Abstract: A method of fabricating a semiconductor integrated circuit comprises the steps of: forming buried layers in predetermined regions of a semiconductor substrate; forming an epitaxial layer covering the substrate and the buried layers; forming isolation regions dividing the epitaxial layer into a plurality of islands; selectively implanting ions to form a base region of a vertical bipolar transistor in a surface layer of one island and simultaneously to form a resistor region in a surface layer of another island; and selectively diffusing impurities into a surface layer of the base region, to form an emitter region of the vertical bipolar transistor.Type: GrantFiled: November 15, 1988Date of Patent: February 6, 1990Assignee: Sanyo Electric Co., Ltd.Inventors: Kazuo Takeda, Nobuyuki Sekikawa, Katsuhiro Hayasaka, Chikao Fujunuma, Nobuo Itoh, Tetsuya Kubota
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Patent number: 4225706Abstract: A novel ester of a cephem compound having a carboxyl group at the 4-position in the nucleus; a process for preparing the same by reacting a cephem carboxylic acid or its salt with a halogenide; and a method for removing the protective group for the carboxyl group in the nucleus of a cephem compound by contacting it with an alcohol, or with an organic solvent in the presence of a Lewis acid.Type: GrantFiled: April 21, 1978Date of Patent: September 30, 1980Assignee: Meiji Seika Kaisha Ltd.Inventors: Shigeo Seki, Ken Nishihata, Satoru Nakabayashi, Toshinori Saito, Hitoshi Ikeda, Nobuo Itoh, Shokichi Nakajima, Shunzo Fukatsu
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Patent number: 4159372Abstract: A process for preparing a cephalosporin ester which comprises subjecting an organic halide or an alcohol to reaction with a cephalosporin acid, a cephalosporin acid halide or a salt thereof in the presence of liquid sulfur dioxide.Type: GrantFiled: March 6, 1978Date of Patent: June 26, 1979Assignee: Meiji Seika Kaisha Ltd.Inventors: Shigeo Seki, Satoru Nakabayashi, Ken Nishihata, Nobuo Itoh, Toshinori Saito, Masahiro Onodera, Shunzo Fukatsu