Abstract: To efficiently cool down heat of a heating element 20, this electronic device 100 is provided with a circuit board 10 having a heating element 20 that is attached to a first main surface 11 thereof, a case 30 having an opening part 31 that is formed in a surface facing the heating element 20 and housing a refrigerant COO therein, and a connection part 40 connecting the opening part 31 and the heating element 20 so as to enclose the refrigerant COO, the connecting part has a thickness of at most 0.21 mm.

Abstract: A compound semiconductor device is comprised of: a compound semiconductor layer including a first active layer and a second active layer forming a hetero junction with the first active layer so as to naturally generate a two-dimensional carrier gas channel in the first active layer along the hetero junction; a first electrode formed on the second active layer; a second electrode in ohmic contact with the first active layer and isolated from the first electrode; and a channel modifier for locally changing a part of the first active layer under the channel modifier into a normally-off state, the channel modifier being formed on the second active layer so as to enclose but be isolated from the first electrode and the second electrode.

Abstract: A object is to provide a semiconductor device having normally-off characteristics and capable of easily suppressing field concentration below a side surface of a concave portion. A device includes a nitride-based semiconductor layer having a concave portion formed in a part of one principal surface, a side surface of the concave portion being slanted; a first electrode provided on the principal surface; a second electrode on an opposite side to the first electrode across the concave portion, and provided on the principal surface; an insulating layer formed on both sides of the concave portion in the principal surface; and a control electrode provided on the concave portion and at least a part of the wall surface of the insulating layer on the concave portion-side. A tilt angle of the wall surface of the insulating layer is greater than a tilt angle of the side surface of the concave portion.

Abstract: An object of the present invention is to reduce on-state resistance and increases reliability in a semiconductor device having an electrode formed in a recessed structure. As illustrated in FIG. 1B, a first insulating layer 103 is formed. Then, as illustrated in FIG. 1C, a photolithography process is carried out to form a photoresist pattern 104. Subsequently, as illustrated in FIG. 1D, dry etching is applied to the first insulating layer 103. Then, as illustrated in FIG. 1E, a laminated semiconductor structure is etched. Next, in this state, wet etching is applied to the first insulating layer 103 as illustrated in FIG. 1F. Next, in this state, an electrode material 105 is formed on the entire exposed surface as illustrated in FIG. 1G. Finally, as illustrated in 1H, the photoresist pattern 104 is removed.

Abstract: A semiconductor device 1 includes a substrate 2 having on a main surface thereof a central area and a peripheral area which surrounds the central area and is exposed, a semiconductor layer 4 which is formed on the main surface of the substrate 2, is made of a material harder than the substrate 2, is in the shape of a mesa, and has a steep side over the exposed peripheral area, and an insulating film 12S provided on a side surface of the semiconductor layer 4.

Abstract: A heterojunction field-effect semiconductor device has a main semiconductor region comprising two layers of dissimilar materials such that a two-dimensional electron gas layer is generated along the heterojunction between the two layers. A source and a drain electrode are placed in spaced positions on a major surface of the main semiconductor region and electrically coupled to the 2DEG layer. Between these electrodes, a gate electrode is received in a recess in the major surface of the main semiconductor region via a p-type metal oxide semiconductor film and insulating film, whereby a depletion zone is normally created in the 2DEG layer, making the device normally off. The p-type metal oxide semiconductor film of high hole concentration serves for the normally-off performance of the device with low gate leak current, and the insulating film for further reduction of gate leak current.

Abstract: A compound semiconductor device includes a compound semiconductor layer in which a two-dimensional carrier gas layer is formed, the compound semiconductor layer including a carrier travel layer and a carrier supply layer; first and second main electrodes, which are arranged apart from each other on the compound semiconductor layer, and are ohmically connected to the two-dimensional carrier gas layer; a metal oxide semiconductor film arranged on the compound semiconductor layer between the first main electrode and the second main electrode; and a control electrode arranged on the metal oxide semiconductor film, the control electrode including a titanium film that contacts the metal oxide semiconductor film or a titanium-containing compound film that contacts the metal oxide semiconductor film.

Abstract: A HEMT-type field-effect semiconductor device has a main semiconductor region comprising two layers of dissimilar materials such that a two-dimensional electron gas layer is generated along the heterojunction between the two layers. A source and a drain electrode are placed in spaced positions on a major surface of the main semiconductor region. Between these electrodes, a gate electrode is received in a recess in the major surface of the main semiconductor region via a p-type metal oxide semiconductor film whereby a depletion zone is normally created in the electron gas layer, with a minimum of turn-on resistance and gate leak current.

Abstract: A compound semiconductor device is comprised of: a compound semiconductor layer including a first active layer and a second active layer forming a hetero junction with the first active layer so as to naturally generate a two-dimensional carrier gas channel in the first active layer along the hetero junction; a first electrode formed on the second active layer; a second electrode in ohmic contact with the first active layer and isolated from the first electrode; and a channel modifier for locally changing a part of the first active layer under the channel modifier into a normally-off state, the channel modifier being formed on the second active layer so as to enclose but be isolated from the first electrode and the second electrode.

Abstract: A HEMT-type field-effect semiconductor device has a main semiconductor region comprising two layers of dissimilar materials such that a two-dimensional electron gas layer is generated along the heterojunction between the two layers. A source and a drain electrode are placed in spaced positions on a major surface of the main semiconductor region. Between these electrodes, a gate electrode is received in a recess in the major surface of the main semiconductor region via a p-type metal oxide semiconductor film whereby a depletion zone is normally created in the electron gas layer, with a minimum of turn-on resistance and gate leak current.

Abstract: A HEMT-type field-effect semiconductor device has a main semiconductor region comprising two layers of dissimilar materials such that a two-dimensional electron gas layer is generated along the heterojunction between the two layers. A source and a drain electrode are placed in spaced positions on a major surface of the main semiconductor region. Between these electrodes, a gate electrode is received in a recess in the major surface of the main semiconductor region via a p-type metal oxide semiconductor film whereby a depletion zone is normally created in the electron gas layer, with a minimum of turn-on resistance and gate leak current.

Abstract: A semiconductor device 1 includes a substrate 2 having on a main surface thereof a central area and a peripheral area which surrounds the central area and is exposed, a semiconductor layer 4 which is formed on the main surface of the substrate 2, is made of a material harder than the substrate 2, is in the shape of a mesa, and has a steep side over the exposed peripheral area, and an insulating film 12S provided on a side surface of the semiconductor layer 4.

Abstract: A object is to provide a semiconductor device having normally-off characteristics and capable of easily suppressing field concentration below a side surface of a concave portion. A device includes a nitride-based semiconductor layer having a concave portion formed in a part of one principal surface, a side surface of the concave portion being slanted; a first electrode provided on the principal surface; a second electrode on an opposite side to the first electrode across the concave portion, and provided on the principal surface; an insulating layer formed on both sides of the concave portion in the principal surface; and a control electrode provided on the concave portion and at least a part of the wall surface of the insulating layer on the concave portion-side. A tilt angle of the wall surface of the insulating layer is greater than a tilt angle of the side surface of the concave portion.

Abstract: A semiconductor device 1 includes a substrate 2 having on a main surface thereof a central area and a peripheral area which surrounds the central area and is exposed, a semiconductor layer 4 which is formed on the main surface of the substrate 2, is made of a material harder than the substrate 2, is in the shape of a mesa, and has a steep side over the exposed peripheral area, and an insulating film 12S provided on a side surface of the semiconductor layer 4.

Abstract: An object of the present invention is to reduce on-state resistance and increases reliability in a semiconductor device having an electrode formed in a recessed structure. As illustrated in FIG. 1B, a first insulating layer 103 is formed. Then, as illustrated in FIG. 1C, a photolithography process is carried out to form a photoresist pattern 104. Subsequently, as illustrated in FIG. 1D, dry etching is applied to the first insulating layer 103. Then, as illustrated in FIG. 1E, a laminated semiconductor structure is etched. Next, in this state, wet etching is applied to the first insulating layer 103 as illustrated in FIG. 1F. Next, in this state, an electrode material 105 is formed on the entire exposed surface as illustrated in FIG. 1G. Finally, as illustrated in 1H, the photoresist pattern 104 is removed.

Abstract: A heterojunction field-effect semiconductor device has a main semiconductor region comprising two layers of dissimilar materials such that a two-dimensional electron gas layer is generated along the heterojunction between the two layers. A source and a drain electrode are placed in spaced positions on a major surface of the main semiconductor region and electrically coupled to the 2DEG layer. Between these electrodes, a gate electrode is received in a recess in the major surface of the main semiconductor region via a p-type metal oxide semiconductor film and insulating film, whereby a depletion zone is normally created in the 2DEG layer, making the device normally off. The p-type metal oxide semiconductor film of high hole concentration serves for the normally-off performance of the device with low gate leak current, and the insulating film for further reduction of gate leak current.

Abstract: A semiconductor device 1 includes a substrate 2 having on a main surface thereof a central area and a peripheral area which surrounds the central area and is exposed, a semiconductor layer 4 which is formed on the main surface of the substrate 2, is made of a material harder than the substrate 2, is in the shape of a mesa, and has a steep side over the exposed peripheral area, and an insulating film 12S provided on a side surface of the semiconductor layer 4.

Abstract: A substrate system of the kind having a buffer region interposed between a silicon substrate proper and a nitride semiconductor region in order to make up for a difference in linear expansion coefficient therebetween. Electrodes are formed on the nitride semiconductor layer or layers in order to provide HEMTs or MESFETs. The buffer region is a lamination of a multiplicity of buffer layers each comprising a first, a second, and a third buffer sublayer of nitride semiconductors, in that order from the silicon substrate proper toward the nitride semiconductor region. The three sublayers of each buffer layer contain aluminum in varying proportions including zero. The aluminum proportion of the third buffer sublayer is either zero or intermediate that of the first buffer sublayer and that of the second.

Abstract: A HEMT-type field-effect semiconductor device has a main semiconductor region comprising two layers of dissimilar materials such that a two-dimensional electron gas layer is generated along the heterojunction between the two layers. A source and a drain electrode are placed in spaced positions on a major surface of the main semiconductor region. Between these electrodes, a gate electrode is received in a recess in the major surface of the main semiconductor region via a p-type metal oxide semiconductor film whereby a depletion zone is normally created in the electron gas layer, with a minimum of turn-on resistance and gate leak current.

Abstract: A high electron mobility transistor is disclosed which has a double-layered main semiconductor region formed on a silicon substrate via a multilayered buffer region. The multilayered buffer region is in the form of alternations of an aluminum nitride layer and a gallium nitride layer. The main semiconductor region, buffer region, and part of the substrate taper as they extend away from the rest of the substrate, providing slanting side surfaces. An electroconductive antileakage overlay covers these side surfaces via an electrically insulating overlay. Electrically coupled to the silicon substrate via a contact electrode, the antileakage overlay serves for reduction of current leakage along the side surfaces.