Abstract: A driver circuit suitable for use to secure output characteristics higher than the element breakdown voltage in an output circuit. The driver circuit includes first and second switching elements connected between a first supply voltage and an outward terminal for driving a load, a relaxation voltage applying section for applying a voltage lower than the first supply voltage to a junction point between the first and second switching elements and a back gate of the second switching element, and a control section for turning on the second switching element and then the first switching element in sequence when the driver circuit is turned on, and turning off the first switching element and then the second switching element in sequence when the driver circuit is turned off.

Abstract: One output signal of a D flip-flop circuit FF2 is fed via a wiring W1 back to an input terminal of a D flip-flop circuit FF1, while one output signal of a D flip-flop circuit FF3 is fed via a wiring W2 back to another input terminal of the D flip-flop circuit FF1. One output signal of the D flip-flop circuit FF1 is supplied to an edge-trigger type flip-flop circuit FF4. A NAND circuit NA generates a reset signal in accordance with the output signal of the edge-trigger type flip-flop circuit FF4 and a frequency-dividing switching control signal which changes the frequency-dividing ratio, and sends the reset signal to the D flip-flop circuit FF3. These D flip-flop circuits FF1, FF2, FF3 and FF4 frequency-divide a clock signal by an odd number or an even number. The D flip-flop circuits FF1, FF2, FF3 and FF4 each comprise multiple NOR gates, which each include field-effect transistors.

Abstract: A semiconductor integrated circuit includes a differential transistor circuit having first and second FETs which each include a drain, a source and a gate and whose sources are connected to each other.

Abstract: There is disclosed a digital integrated circuit device which has high-speed transistors of a selected type. A timing controller is incorporated in this device and performs timing control for an internal digital circuit. The timing controller includes a series-circuit of two flip-flop circuits serving as a frequency-dividing circuit for frequency-dividing a reference clock signal and generating an internal timing signal, and a switch circuit connected to a signal feedback line of these flip-flop circuits. In a normal mode, the switch circuit supplies the internal timing signal output from the flip-flop circuits to the digital integrated circuit. At a desired timing, the switch circuit performs a switching operation in response to a control signal, electrically disconnects the signal feedback line of the flip-flop circuits, and alternatively supplies an external timing signal externally supplied thereto to the digital integrated circuit.