Abstract: A content distribution system according to an embodiment is provided with at least one processor. The at least one processor: specifies a real image region and a farthest region in a space represented with a content image showing a first virtual object; disposes a second virtual object in the farthest region; and displays, on a user terminal, a content image representing a space in which the second virtual object is disposed.

Abstract: Provided is a content distribution server which is able to establish restrictions on the public disclosure of an object displayed in virtual space at the convenience of the distributor. The content distribution server comprises: a distribution unit that distributes live content for synthesizing video in virtual space using information from the distributor as virtual character information; and a first setting receiving unit that receives from the distributor terminal used by the distributor public disclosure restriction settings for establishing restrictions on objects present in virtual space displayed on the distributor terminal that can be viewed on a viewer terminal used by a viewer to view live content.

Abstract: A video distribution server, video distribution method, and recording medium which receives moving images from an originating terminal and distributes these moving images to a viewer terminal implements a questionnaire within the broadcast on the basis of commands from the originating terminal and provides the same questionnaire to a Web server.

Abstract: A valve in an embodiment includes: a valve box in which valve box seat portions are provided; and a valve element on which valve element seat portions are provided. One of the valve box seat portion and the valve element seat portion is formed of a build-up material of a Co-based alloy and the other of the valve box seat portion and the valve element seat portion is formed of a build-up material of an Fe-based alloy. Then, a Vickers hardness of the build-up material of the Co-based alloy is larger than a Vickers hardness of the build-up material of the Fe-based alloy and a difference in the Vickers hardness between the build-up material of the Co-based alloy and the build-up material of the Fe-based alloy is HV50 or more.

Abstract: Provided is a magnet structure (MS) which includes a plurality of permanent magnets (2) fixed onto a baseplate (1), and a cover structure (3) for covering the plurality of permanent magnets (2). The cover structure (3) includes a plurality of covers (3a) that is formed of a non-magnetic material and covers the plurality of permanent magnets (2). A relative position between the plurality of covers (3a) is fixed, and there is a gap (G) between the neighboring covers (3a).

Abstract: An object is to provide an electromagnetic actuator that is highly resistant to corrosion and also capable of having high suction power, even in a condition where part of the electromagnetic actuator touches a corrosive liquid. An electromagnetic actuator 50 according to this invention is incorporated into a device using a corrosive liquid 17.

Abstract: An object is to provide an electromagnetic actuator that is highly resistant to corrosion and also capable of having high suction power, even in a condition where part of the electromagnetic actuator touches a corrosive liquid. An electromagnetic actuator 50 according to this invention is incorporated into a device using a corrosive liquid 17.

Abstract: A four-input to two-output adder is disclosed. The four-input/two-output adder includes a sum-lookahead full adder and a modified full adder. The sum-lookahead full adder includes an XOR3 block and an AXOR block for receiving a first input, a second input, a third input, and an input from a forward adjacent adder to generate a first sum signal and a sum-lookahead carry signal, respectively. The modified full adder includes an XOR2 block and a MUX2 block for receiving the first sum signal from the sum-lookahead-full adder, a fourth input, and a sum-lookahead carry signal from a backward adjacent adder to generate a second sum signal and a carry signal, respectively.

Abstract: A five-input/two-output binary adder is disclosed. The five-input/two-output adder includes five inputs and two outputs. Four levels of XOR logic gates are coupled between the five inputs and the two outputs for combining values received at the five inputs and generating a sum value and a carry value at the outputs.

Abstract: A new D-type latch structure is disclosed which has an input data sampling circuit and a symmetrical cross coupled latching circuit. The clock is delayed a predetermined time through an inverter circuit. The clock and the delayed inverted clock are used to generate a clock window time during which time the data input state and the inverted data input state are asserted on the latch output and complementary. The latch outputs are cross-coupled to pull-up and pull-down circuitry in each output circuit stage. A common pull-down transistor may be used to further reduce devices and to improve path delays from clocks to the latch outputs. The clock window assertion of states of the data inputs to the changing latch output is enhanced by the cross-coupled feedback of the latch outputs to improve the differential transition timings of the latch outputs. The D-type latch has fewer transistors and better delay, and more precise transition skew over prior art designs.

Abstract: A new D-type latch structure is disclosed which has an input data sampling circuit and a symmetrical cross coupled latching circuit. The clock is delayed a predetermined time through an inverter circuit. The clock and the delayed inverted clock are used to generate a clock window time during which time the data input state and the inverted data input state are asserted on the latch output and complementary. The latch outputs are cross-coupled to pull-up and pull-down circuitry in each output circuit stage. A common pull-down transistor may be used to further reduce devices and to improve path delays from clocks to the latch outputs. The clock window assertion of states of the data inputs to the changing latch output is enhanced by the cross-coupled feedback of the latch outputs to improve the differential transition timings of the latch outputs. The D-type latch has fewer transistors and better delay, and more precise transition skew over prior art designs.

Abstract: An edge-triggered latch that incorporates pass-transistor logic (PTL) in the data and clock generation paths. In accordance with one embodiment, an edge-triggered latch includes a data input and at least one data path PTL transistor that passes data from the data input into a storage node in response to a latch trigger signal. A latch trigger circuit generates the latch-trigger signal in response to a clock signal transition.

Abstract: A processor cycle time independent pipeline cache and method for pipelining data from a cache provide a processor with operand data and instructions without introducing additional latency for synchronization when processor frequency is lowered or when a reload port provides a value a cycle earlier than a read access from the cache storage. The cache incorporates a persistent data bus that synchronizes the stored data access with the pipeline and can also utilize bypass mode data available from a cache input from the lower level when data is being written to the cache.

Abstract: An edge-triggered latch that incorporates pass-transistor logic (PTL) in the data and clock generation paths. In accordance with one embodiment, an edge-triggered latch includes a data input and at least one data path PTL transistor that passes data from the data input into a storage node in response to a latch trigger signal. A latch trigger circuit generates the latch-trigger signal in response to a clock signal transition.

Abstract: A new D-type latch structure is disclosed which has an input data sampling circuit and a symmetrical cross coupled latching circuit. The clock is delayed a predetermined time through an inverter circuit. The clock and the delayed inverted clock are used to generate a clock window time during which time the data input state and the inverted data input state are asserted on the latch output and complementary. The latch outputs are cross-coupled to pull-up and pull-down circuitry in each output circuit stage. A common pull-down transistor may be used to further reduce devices and to improve path delays from clocks to the latch outputs. The clock window assertion of states of the data inputs to the changing latch output is enhanced by the cross-coupled feedback of the latch outputs to improve the differential transition timings of the latch outputs. The D-type latch has fewer transistors and better delay, and more precise transition skew over prior art designs.

Abstract: An edge-triggered latch having improved clock-to-output performance and greater efficiency. The edge-triggered latch of the present invention includes a data input and a clock input. Multiple source-to-drain connected pass-transistor logic (PTL) transistors are incorporated in the data path of the edge-triggered latch for converting a clock signal from the clock input into an edge-triggered data evaluation window. The PTL transistors propagate data from the data input into a storage node during the edge-triggered data evaluation window.

Abstract: A set-associative cache memory having a built-in set prediction array is disclosed. The cache memory can be accessed via an effective address having a tag field, a line index field, and a byte field. The cache memory includes a directory, a memory array, a translation lookaside buffer, and a set prediction array. The memory array is associated with the directory such that each tag entry within the directory corresponds to a cache line within the memory array. In response to a cache access by an effective address, the translation lookaside buffer determines whether or not the data associated with the effective address is stored within the memory array. The set prediction array is built-in within the memory array such that an access to a line entry within the set prediction array can be performed in a same access cycle as an access to a cache line within the memory array.

Abstract: A true/complement signal generator for a dynamic logic circuit having a dynamic node is disclosed. The true/complement signal generator for a dynamic logic circuit having a dynamic node includes a cascaded inverter circuit, a first half-latch circuit, and a second half-latch circuit. The cascaded inverter circuit, which is connected to the dynamic node, includes a first inverter connected in series with a second inverter. Connected to an output of the second inverter of the cascaded inverter circuit, the first half-latch circuit generates an output signal. Connected to an output of the first inverter of the cascaded inverter circuit, the second half-latch circuit generates a complement output signal.

Abstract: A flue gas treatment system is provided for which is capable of easily treating Se contained in flue gas, comprising an extractor 13 for extracting soluble components in the dust removed by a dry-type dust precipitator 5 into water to slurry the dust; insolubilizer supply 16 for supplying an insolubilizer for insolubilizing at least tetravalent Se to the dust slurry which has been slurried from the dust by the extractor 13; adsorbent supply 14 for supplying an adsorbent composed of an organism material for adsorbing at least hexavalent Se in the dust slurry; and separator 15 for solid-liquid separating the dust slurry to which the insolubilizer and the adsorbent have been supplied by said supplies.

Abstract: A process for the carboxylation and/or alkoxycarbonylation of olefins with carbon monoxide and water or alcohol in the presence of cobalt carbonyl catalyst and also vinyl pyridine together with pyridine and/or alkyl pyridine, is disclosed.