Abstract: A pulse generation circuit including a pulse formation circuit for generating normal and dummy pulses according to second delay value data, a data calculation circuit for calculating first delay value data at a timing at which the pulses are generated from the pulse formation circuit according to pattern data having information for determining whether to generate pulses from the pulse formation circuit, a dummy pulse control circuit for controlling generation of a dummy pulse in a no-pulse-generation cycle from the pulse formation circuit according to the second delay value data obtained by detecting the no-pulse-generation cycle from the first delay value data, and a logical gate circuit for eliminating the dummy pulses generated from the pulse formation circuit.

Abstract: In an odd side storage circuit, logical values of a decision subject signal HCMP are stored in first and second FFs respectively at decision edges LH and HL generated from odd-numbered edges of a decision edge EH. Logical values of a delayed decision subject signal HCMP′ are stored in third and fourth FFs. According to a selection signal generated by a selection signal generation circuit based on outputs of the third and fourth FFs, a first selector selects an output of the first or second FF. An even side storage circuit operates similarly at even-numbered edges. A second selector selects the odd and even side storage circuits alternately. The FFs in the odd and even side storage circuits are reset by a decision edge LH′ of the even side and the decision edge HL of the odd side, respectively.

Abstract: In an odd side storage circuit, logical values of a decision subject signal HCMP are stored in first and second FFs respectively at decision edges LH and HL generated from odd-numbered edges of a decision edge EH. Logical values of a delayed decision subject signal HCMP′ are stored in third and fourth FFs. According to a selection signal generated by a selection signal generation circuit based on outputs of the third and fourth FFs, a first selector selects an output of the first or second FF. An even side storage circuit operates similarly at even-numbered edges. A second selector selects the odd and even side storage circuits alternately. The FFs in the odd and even side storage circuits are reset by a decision edge LH′ of the even side and the decision edge HL of the odd side, respectively.

Abstract: In an odd side storage circuit, logical values of a decision subject signal HCMP are stored in first and second FFs respectively at decision edges LH and HL generated from odd-numbered edges of a decision edge EH. Logical values of a delayed decision subject signal HCMP′ are stored in third and fourth FFs. According to a selection signal generated by a selection signal generation circuit based on outputs of the third and fourth FFs, a first selector selects an output of the first or second FF. An even side storage circuit operates similarly at even-numbered edges. A second selector selects the odd and even side storage circuits alternately. The FFs in the odd and even side storage circuits are reset by a decision edge LH′ of the even side and the decision edge HL of the odd side, respectively.

Abstract: The present invention provides a pulse generation circuit comprising: a pulse formation circuit for generating normal and dummy pulses according to second delay value data; a data calculation circuit for calculating first delay value data being shown a timing at which the pulses is generated from the pulse formation circuit according to pattern data that has information for determining whether to generate pulses from the pulse formation circuit; a dummy pulse control circuit for controlling generation of a dummy pulse in a no-pulse-generation cycle from the pulse formation circuit according to the second delay value data obtained by detecting said no-pulse-generation cycle from said first delay value data; and a logical gate circuit for eliminating the dummy pulses generated from the pulse formation circuit, being disposed between said pulse formation circuit.

Abstract: In an odd side storage circuit, logical values of a decision subject signal HCMP are stored in first and second FFs respectively at decision edges LH and HL generated from odd-numbered edges of a decision edge EH. Logical values of a delayed decision subject signal HCMP′ are stored in third and fourth FFs. According to a selection signal generated by a selection signal generation circuit based on outputs of the third and fourth FFs, a first selector selects an output of the first or second FF. An even side storage circuit operates similarly at even-numbered edges. A second selector selects the odd and even side storage circuits alternately. The FFs in the odd and even side storage circuits are reset by a decision edge LH′ of the even side and the decision edge HL of the odd side, respectively.