Patents by Inventor Nobuo Nagano

Nobuo Nagano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7714269
    Abstract: A light receiving circuit according to the present invention includes a current control voltage generation circuit 10 outputting control voltages Vcont1 and Vcont2, a first current adjusting circuit 11 generating a first output current Io1 by regulating a first input current Ii1 depending on a voltage difference of the control voltages Vcont1 and Vcont2, the first input current Ii1 generated by adding a first reference current Ia1 and an input current Ipd, a second current adjusting circuit 12 generating a second output current Io2 by regulating a second reference current Ia2 depending on the voltage difference of the control voltages Vcont1 and Vcont2, and a current voltage conversion circuit 13 generating a first output voltage Vo1 by converting the first output current Io1 to voltage based on a first resistance Rf1 and generating a second output voltage Vo2 by converting the second output current Io2 to voltage based on a second resistance Rf2.
    Type: Grant
    Filed: February 1, 2008
    Date of Patent: May 11, 2010
    Assignee: NEC Electronics Corporation
    Inventors: Kei Yoshikawa, Ryusuke Shibata, Tokio Sawataishi, Nobuo Nagano, Koichi Iguchi
  • Publication number: 20080197890
    Abstract: A light receiving circuit according to the present invention includes a current control voltage generation circuit 10 outputting control voltages Vcont1 and Vcont2, a first current adjusting circuit 11 generating a first output current Io1 by regulating a first input current Ii1 depending on a voltage difference of the control voltages Vcont1 and Vcont2, the first input current Ii1 generated by adding a first reference current Ia1 and an input current Ipd, a second current adjusting circuit 12 generating a second output current Io2 by regulating a second reference current Ia2 depending on the voltage difference of the control voltages Vcont1 and Vcont2, and a current voltage conversion circuit 13 generating a first output voltage Vo1 by converting the first output current Io1 to voltage based on a first resistance Rf1 and generating a second output voltage Vo2 by converting the second output current Io2 to voltage based on a second resistance Rf2.
    Type: Application
    Filed: February 1, 2008
    Publication date: August 21, 2008
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Kei Yoshikawa, Ryusuke Shibata, Tokio Sawataishi, Nobuo Nagano, Koichi Iguchi
  • Patent number: 6661252
    Abstract: A matrix switch device comprises a semiconductor integrated circuit chip comprising a 2×2 matrix switch having two input terminals and two output terminals and an SPDT switch at a stage subsequent to the 2×2 matrix switch, the SPDT switch having two input terminals and one output terminal, wherein electrical connection is performed between one of the output terminals of the 2×2 matrix switch and one of the input terminals of the SPDT switch, and wherein the two input terminals and the other of said output terminals of the 2×2 matrix switch, and the other input terminal and the output terminal of the SPDT switch are led out of the semiconductor integrated circuit chip.
    Type: Grant
    Filed: July 3, 2002
    Date of Patent: December 9, 2003
    Assignees: NEC Compound Semiconductor Devices, Ltd., Sharp Kabushiki Kaisha
    Inventors: Nobuo Nagano, Kazuhiko Onda, Junichi Somei
  • Publication number: 20030016071
    Abstract: A matrix switch device comprises a semiconductor integrated circuit chip comprising a 2×2 matrix switch having two input terminals and two output terminals and an SPDT switch at a stage subsequent to the 2×2 matrix switch, the SPDT switch having two input terminals and one output terminal, wherein electrical connection is performed between one of the output terminals of the 2×2 matrix switch and one of the input terminals of the SPDT switch, and wherein the two input terminals and the other of said output terminals of the 2×2 matrix switch, and the other input terminal and the output terminal of the SPDT switch are led out of the semiconductor integrated circuit chip.
    Type: Application
    Filed: July 3, 2002
    Publication date: January 23, 2003
    Inventors: Nobuo Nagano, Kazuhiko Onda, Junichi Somei
  • Patent number: 6467666
    Abstract: A method of producing a semiconductor device of the present invention is applicable to a multilayer wafer for leadless chip carrier packages and breaks it on a package basis. The method begins with a step of forming a generally V-shaped groove in one major surfaces of the wafer in the direction of thickness of the wafer. A weak, cleaving portion is formed in the other major surface of the wafer in alignment with the groove. A cleaving force is exerted on the wafer to thereby form a break in the cleaving portion, so that the wafer is caused to break from the groove toward the cleaving portion in the direction of thickness of the wafer. The cleaving portion may be replaced with a strong, non-cleaving portion, in which case the break is formed in the interface between the non-cleaving portion and the wafer due to a difference in cleaving force.
    Type: Grant
    Filed: May 30, 2001
    Date of Patent: October 22, 2002
    Assignee: NEC Corporation
    Inventors: Seiji Ichikawa, Tatsuo Tokue, Nobuo Nagano, Fumie Ogihara, Taku Sato
  • Publication number: 20010048014
    Abstract: A method of producing a semiconductor device of the present invention is applicable to a multilayer wafer for leadless chip carrier packages and breaks it on a package basis. The method begins with a step of forming a generally V-shaped groove in one major surfaces of the wafer in the direction of thickness of the wafer. A weak, cleaving portion is formed in the other major surface of the wafer in alignment with the groove. A cleaving force is exerted on the wafer to thereby form a break in the cleaving portion, so that the wafer is caused to break from the groove toward the cleaving portion in the direction of thickness of the wafer. The cleaving portion may be replaced with a strong, non-cleaving portion, in which case the break is formed in the interface between the non-cleaving portion and the wafer due to a difference in cleaving force.
    Type: Application
    Filed: May 30, 2001
    Publication date: December 6, 2001
    Applicant: NEC Corporation
    Inventors: Seiji Ichikawa, Tatsuo Tokue, Nobuo Nagano, Fumie Ogihara, Taku Sato