Patents by Inventor Nobuo Shimotsuma

Nobuo Shimotsuma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4217540
    Abstract: A voltage regulating circuit for supplying a regulated voltage to an electronic circuit of an electronic timepiece. The voltage regulating circuit is comprised of an N-MOS and a P-MOS transistor pair connected in series with drains and gates connected together at a common junction, and a constant current source for providing a constant current through the transistor pair for developing the regulated voltage thereacross. The constant current source is comprised of a third MOS transistor connected in series with the transistor pair, and a biasing circuit for biasing the third MOS transistor to provide a constant current through the transistor pair. The voltage regulating circuit and the electronic circuit of the electronic timepiece are both integrated circuits formed on a common integrated circuit chip.
    Type: Grant
    Filed: June 23, 1978
    Date of Patent: August 12, 1980
    Assignee: Kabushiki Kaisha Daini Seikosha
    Inventor: Nobuo Shimotsuma
  • Patent number: 4138841
    Abstract: An electronic timepiece comprising an oscillating circuit for producing a standard time signal, a dividing circuit for dividing the output signal of said oscillating circuit and a driving circuit. The output signal of said driving circuit is controlled by a controlling circuit cooperative with the dividing circuit for changing the division of the standard time signal.
    Type: Grant
    Filed: November 3, 1976
    Date of Patent: February 13, 1979
    Assignee: Kabushiki Kaisha Daini Seikosha
    Inventors: Shojiro Komaki, Nobuo Shimotsuma
  • Patent number: 4128816
    Abstract: An electronic circuit which has a constant voltage circuit comprises a reference voltage generating circuit, a voltage controlled element receiving the signals from said reference voltage generating circuit which is composed of a plurality of MOS transistors, and a load circuit receiving said constant voltage circuit.
    Type: Grant
    Filed: July 18, 1977
    Date of Patent: December 5, 1978
    Assignee: Kabushiki Kaisha Daini Seikosha
    Inventor: Nobuo Shimotsuma