Abstract: A semiconductor device having a fuse has a fuse and a resistance connected in series between power-supply potential and ground and decides whether the fuse is fused in accordance with the potential of the connection point between the fuse and the resistance connected in series between the power-supply potential and the ground under the normal operating state. A decision circuit is included whose input terminal is connected to the connection point between the fuse and the resistance to decide whether the fuse is fused. A switching circuit is included which connects a test resistance in parallel with the fuse at the time of a test but does not connect the test resistance under the normal state and at the time of the test, a fuse resistance value in a range wider than the range for deciding whether a fuse is fused under the normal state is decided to be defective to decide whether the fuse is fused.

Abstract: A reset circuit includes a plurality of registers (R1-R8) in which a logical value at power on is shifted and set to a predetermined logical value after a predetermined time has elapsed since a power supply was switched on and a logic circuit (1) for outputting a coincidence signal while each of the/plurality of registers is set to the predetermined logic value but outputting a non-coincidence signal while when at least one register is set to a value different from the predetermined logical value. The non-coincidence signal is employed as a reset signal. The plurality of registers are designed to output a value different from the predetermined logic value initially when switching on the power supply. The reset signal can be obtained by even a low power voltage irrespective of a power voltage waveform at the power-on time.

Abstract: A semiconductor memory device comprises a memory cell array formed by arranging a plurality of rewritable non-volatile memory cells in matrix form and in correspondence to address lines and bit positions so as to be connected to erase and write lines via select gate transistors; and a controller for applying a rewriting voltage to any one of each erase line and each write line according to each bit logical value of an input data or according to each bit logical value of each selected bit of an input data in order to execute data rewrite operation. Since data rewrite operation can be executed to only the memory cells belonging to an address and required to be rewritten without once erasing all the memory cells, the data rewriting speed can be increased. By another aspect, the controller applies predetermined high voltage only for memory cells selected according to bit selection, resulting in longer lifetime of the memory cells.

Abstract: A semiconductor memory device includes a plurality of memory cells arranged in rows and columns, a plurality of bit lines, each coupled to the memory cells forming one column, and a MOS transistor connected between a power supply terminal and one end of every bit line. The device further includes at least one test memory cell coupled in series with the MOS transistor, thus forming a series circuit connected between the power supply terminal and the ground.