Abstract: A semiconductor memory device having a plurality of memory cells each comprising two CMOS inverters cross-coupled to each other and arranged at intersections between a plurality of word lines extending in a column direction and a plurality of complementary data line pairs extending in a row direction; wherein p-channel type load MISFETs of the memory cells arranged in the column direction are formed on the main surface of an n-type well region in the direction in which the word lines extend, the source regions of the p-channel type load MISFETs of the memory cells arranged in the column direction are electrically connected to the n-type well region through conductor layers, and each of the conductor layer is formed independently of the memory cells arranged in the column direction.

Abstract: A variable logic circuit comprises a memory cell, a transistor which turns on or off depending on data stored in the memory cell, a transistor which is connected in series to the above-mentioned transistor and is turned on or off by an input signal, a transistor which produces a voltage depending on the conduction states of the above-mentioned transistors, and transfer means which conducts or does not conduct the produced voltage to the output terminal depending on a select signal.

Abstract: A variable logic integrated circuit device formed on a semiconductor chip comprising variable logic blocks and switch matrices laid out alternately in the X and Y directions in a checkerboard pattern. Above the variable logic blocks is a block interconnection wiring arrangement formed by multiple-layer wiring techniques. The variable logic blocks and switch matrices are wired into circuits respectively by a lower wiring layer in the multiple wiring layer setup of the chip. The block interconnection wiring is formed by an upper wiring layer extending above the variable logic blocks and included in the multiple wiring layer setup. The switch matrices are used to connect the block interconnection lines to one another as well as to the variable logic blocks.

Abstract: A semiconductor integrated circuit device includes an element separating first and second grooves formed to surround active regions to be formed with a semiconductor element. In addition a third groove is formed to surround at least a portion of the first groove, when viewed from a plane view. In the semiconductor integrated circuit device, the active regions and an element separating region of a silicon layer are insulated from each other by the separating grooves extending from the main surface of the silicon layer to an underlying insulating layer, and are fed with a common fixed potential.

Abstract: A programmable two-line, two-phase logic array has a plurality of inputs, each having two input signals operating in two phases and memory cells provided at an intersection of the input signal lines and output lines corresponding to at least one function that cross the input lines. The memory cells are capable of being written in the fabrication process or by a field programming process that addresses the contact points at which the input and output lines cross. The two-line, two-phase logic circuit can be attained by the same technique as that used for attaining a conventional PLA without designing circuitry based on a conventional synchronous logic beforehand followed by replacing it with a two-line, two-phase circuit.

Abstract: A semiconductor memory device having a plurality of memory cells each comprising two CMOS inverters cross-coupled to each other and arranged at intersections between a plurality of word lines extending in a column direction and a plurality of complementary data line pairs extending in a row direction; wherein p-channel type load MISFETs of the memory cells arranged in the column direction are formed on the main surface of an n-type well region in the direction in which the word lines extend, the source regions of the p-channel type load MISFETs of the memory cells arranged in the column direction are electrically connected to the n-type well region through conductor layers, and each of the conductor layer is formed independently of the memory cells arranged in the column direction.

Abstract: Disclosed are a semiconductor integrated circuit device and methods for production thereof. An embodiment of the invention is a semiconductor chip that comprises fuses constituting part of redundancy circuits formed therein, the fuses being made of the same ingredients CCB bump substrate metal. The fuses are patterned simultaneously during the patterning of the CCB bump substrate metal. This involves forming the fuses using at least part of the ingredients of an electrode conductor pattern in the chip. The cutting regions of the fuses are made of only one of the metal layers constituting the substrate. The principal plane of the semiconductor chip has a fuse protective film formed over at least the cutting regions of the fuses for protection of the latter. In operation, a switch MOSFET under switching control of a redundancy signal is used to select one of two transmission paths, one carrying an address signal or a decode signal, the other carrying a reference voltage.

Abstract: Disclosed is a bipolar-CMOS LSI manufactured by a simplified process and realizing a higher density of integration as well as a higher operating speed, in which a base lead-out electrode of a bipolar transistor and respective gate electrodes of a p-channel MISFET and an n-channel MISFET of CMOS transistors are made of an identical conductor film, and the conductor film of the gate electrode of the p-channel MISFET is of p-type, while that of the gate electrode of the n-channel MISFET is of n-type.

Abstract: A semiconductor integrated circuit device is provided for permitting operation of a CMOS or BiCMOS memory with ECL level input signals, in which operating speed is increased and power consumption is reduced.Input signals of ECL levels are received by an input buffer for amplifying the input signals to an output signal level within a range where differential transistors of the input buffer operate in an unsaturation region. The output signal of the input buffer is supplied to a CMOS circuit or Bi-CMOS circuit which is operated by both an operating voltage having a first-stage smaller absolute value than that of the operating voltage of the input buffer and the ground potential of the circuit. This first stage CMOS or BiCMOS circuit also includes an arrangement to further amplify the received signals to provide further level conversion.

Abstract: Disclosed are a semiconductor integrated circuit device and methods for production thereof. An embodiment of the invention is a semiconductor chip that comprises fuses constituting part of redundancy circuits formed therein, the fuses being made of the same ingredients as those of a CCB bump substrate metal. The fuses are patterned simultaneously during the patterning of the CCB bump substrate metal. This involves forming the fuses using at least part of the ingredients of an electrode conductor pattern in the chip. The cutting regions of the fuses are made of only one of the metal layers constituting the substrate. The principal plane of the semiconductor chip has a fuse protective film formed over at least the cutting regions of the fuses for protection of the latter. In operation, a switch MOSFET under switching control of a redundancy signal is used to select one of two transmission paths, one carrying an address signal or a decode signal, the other carrying a reference voltage.

Abstract: Disclosed is a bipolar-CMOS LSI manufactured by a simplified process and realizing a higher density of integration as well as a higher operating speed, in which a base lead-out electrode of a bipolar transistor and respective gate electrodes of a p-channel MISFET and an n-channel MISFET of CMOS transistors are made of an identical conductor film, and the conductor film of the gate electrode of the p-channel MISFET is of p-type, while that of the gate electrode of the n-channel MISFET is of n-type.

Abstract: A semiconductor integrated circuit device including a level conversion circuit in which the simplifying of the circuit and the increasing of the speed of operation have been attained is provided.A pair of complementary output signals amplified to a required signal level by a current switch circuit including differential transistors which receive an input signal and a reference voltage are inputted into a pair of emitter follower circuits. An emitter follower output transistor is driven by an output signal from one emitter follower circuit, while an N-channel MOSFET provided between the output transistor and a current source used as a load is driven by an output signal from the other emitter follower circuit, to obtain a level-amplified output signal from an emitter of the output transistor.

Abstract: A semiconductor integrated circuit device having a structure in which each of the following regions, that is, a first region for forming the base and emitter regions of each of the bipolar transistors, a second region for forming the collector lead-out region of the bipolar transistor, and a third region for forming each of the MISFETs, is projected from the main surface of a semiconductor substrate, whereby it is possible to effect isolation between the MISFETs and between these MISFETs and the bipolar transistors with the same isolation structure and in the same manufacturing step as those for the isolation between the bipolar transistors. In this device, furthermore, the base region of the bipolar transistor is electrically and self-alignedly connected to a base electrode which is formed over the main surface so as to surround the emitter region.

Abstract: Disclosed is a bipolar-CMOS LSI manufactured by a simplified process and realizing a higher density of integration as well as a higher operating speed, in which a base lead-out electrode of a bipolar transistor and respective gate electrodes of a p-channel MISFET and an n-channel MISFET of CMOS transistors are made of an identical conductor film, and the conductor film of the gate electrode of the p-channel MISFET is of p-type, while that of the gate electrode of the n-channel MISFET is of n-type.

Abstract: In a semiconductor integrated circuit device having memory cell arrays, power source wirings are provided on the memory cell array in parallel with the long side of the memory cell array, thereby strengthening the power source wirings without increasing a chip size and planning reduction in power source impedances.

Abstract: In a semiconductor integrated circuit device, input protective elements have current limiting resistors which are diffused resistors of a second conductivity type formed in a first semiconductor region of a first conductivity type isolated electrically by a second semiconductor region of the second conductivity type, with the first conductivity type semiconductor region being in a floating state electrically. The input protective elements create less leak current and have high electrostatic durability.

Abstract: A semiconductor memory device having a plurality of memory cells each comprising two CMOS inverters cross-coupled to each other and arranged at intersections between a plurality of word lines extending in a column direction and a plurality of complementary data line pairs extending in a row direction; wherein p-channel type load MISFETs of the memory cells arranged in the column direction are formed on the main surface of an n-type well region in the direction in which the word lines extend, the source regions of the p-channel type load MISFETs of the memory cells arranged in the column direction are electrically connected to the n-type well region through conductor layers, and each of the conductor layer is formed independently of the memory cells arranged in the column direction.