Abstract: A semiconductor device such as a MIS type capacitor which including a semiconductor substrate of one conductive sign (p-type silicon substrate), a region (n-type) of conductive sign opposite to that of the substrate formed in the substrate, an electrode making up a capacitor formed on the substrate apart from the region of opposite conductive sign and a transfer gate formed between the capacitor and the region of opposite conductive sign. The device is fabricated according to the invention such that the insulating film is formed under the electrode and has substantially the same planar form as the electrode, the insulating film contains impurities of a conductive sign opposite to that of the substrate and the region of opposite conductive sign is formed where the insulating film is in contact with the substrate. The region of opposite conductive sign is formed accurately in a self-alignment fashion.

Abstract: A thin film resistor for use in microelectronic devices, the resistor having a resistive layer comprising silicon nitride (Si.sub.3 N.sub.4) and refractory metals of tungsten and/or molybdenum. The features of the structure of the resistor is that the film comprises a silicon nitride layer and grains of metal and/or metal silicide, wherein the resistivity is determined mainly by the silicon nitride. Therefore, the total resistance of the resistor can be controlled by controlling the amount of the silicon nitride, thus providing a wide range of the resistivity of 10.sup.-3 to 10.sup.9 .OMEGA.cm. Other characteristics such as immunity to the dopant contained in an adjacent doped layer, namely heat resistivity and low activation energy of the resistivity are verified by associated experiments.

Abstract: A method for producing semiconductor devices having a substrate, element fabrication areas formed in the substrate and isolation areas surrounding the element fabrication areas. The method comprises forming a thermal strain absorbing layer on the top surface of the element fabrication areas, forming at least one groove in an area which is to become the isolation areas, inlaying an insulator in the at least one groove, and annealing the insulator to make the density thereof uniform.

Abstract: A process for producing a dielectric layer which on a semiconductor layer comprises the steps of forming a layer of oxide of an element selected from the group consisting of tantalum, titanium, niobium, hafnium, yttrium, zirconium, and vanadium on the surface of the semiconductor layer and heating the semiconductor layer having the oxide layer thereon in an oxidizing atmosphere. The semiconductor layer is thermally oxidized so as to form an insulating layer which comprises oxide of the semiconductor material at the interface between the semiconductor layer and the oxide layer.

Abstract: A metal layer of a metal-insulator-semiconductor type semiconductor device, e.g., a metal electrode on an oxide layer covering a semiconductor substrate of an MOS diode or an MOS FET, contains at least one cation-trapping element. The semiconductor substrate with the metal layer and the oxide layer is heated at an elevated temperature to diffuse some of the ions responsible for the cation-trapping element out of the metal layer and into the upper part of the oxide layer. The metal and oxide layers promote the surface passivation of the semiconductor device.

Abstract: A metal layer of a metal-insulator-semiconductor type semiconductor device, e.g., a metal electrode on an oxide layer covering a semiconductor substrate of an MOS diode or an MOS FET, contains at least one cation-trapping element. The semiconductor substrate with the metal layer and the oxide layer is heated at an elevated temperature to diffuse some of the ions responsible for the cation-trapping element out of the metal layer and into the upper part of the oxide layer. The metal and oxide layers promote the surface passivation of the semiconductor device.