Patents by Inventor Nobuo Tsuboi
Nobuo Tsuboi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11945535Abstract: A leaning vehicle including a vehicle body frame that is configured to lean leftward and rightward respectively when the leaning vehicle is turning left and right, a steerable wheel supported by the vehicle frame body, a steering mechanism steering the steerable wheel, and a posture control actuator device. The posture control actuator device includes a posture control actuator that outputs power to control posture of the vehicle body frame, and an angular rate sensor that detects an amount of change per unit time of a rotation angle of the vehicle body frame around a rotation axis thereof, the rotation angle changing as the vehicle body frame is rotating around the rotation axis. The posture control actuator device is supported by the vehicle body frame, and is attachable to and detachable from the vehicle body frame. The posture control actuator and the angular rate sensor are not displaceable relative to each other.Type: GrantFiled: February 25, 2021Date of Patent: April 2, 2024Assignee: YAMAHA HATSUDOKI KABUSHIKI KAISHAInventors: Nobuo Hara, Hidekazu Tsuboi
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Patent number: 11031304Abstract: To improve a reliability of a semiconductor device, a memory cell array is formed in a product region of an SOI substrate, and a test cell array is formed in a scribe region of the SOI substrate. A plurality of regions is formed in each of the memory cell array and the test cell array. The plurality of regions formed in the test cell array is the same configuration as the plurality of regions formed in the memory cell array. A plurality of plugs is formed in the plurality of regions, respectively. Also, it can determine whether or not a leak path is occurred in the memory cell array, by inspecting whether or not a conduction between the plurality of plugs is confirmed.Type: GrantFiled: April 20, 2020Date of Patent: June 8, 2021Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Nobuo Tsuboi
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Publication number: 20200411383Abstract: To improve a reliability of a semiconductor device, a memory cell array is formed in a product region of an SOI substrate, and a test cell array is formed in a scribe region of the SOI substrate. A plurality of regions is formed in each of the memory cell array and the test cell array. The plurality of regions formed in the test cell array is the same configuration as the plurality of regions formed in the memory cell array. A plurality of plugs is formed in the plurality of regions, respectively. Also, it can determine whether or not a leak path is occurred in the memory cell array, by inspecting whether or not a conduction between the plurality of plugs is confirmed.Type: ApplicationFiled: April 20, 2020Publication date: December 31, 2020Inventor: Nobuo TSUBOI
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Patent number: 10811432Abstract: There is provided with the following semiconductor device to improve its reliability. In a SOI substrate including a semiconductor substrate, an insulating layer, and a semiconductor layer, a diffusion region is formed in the semiconductor layer and a plug electrically connected to the diffusion region is formed on the diffusion region. An element isolation portion is formed within the semiconductor substrate and a trench is formed in the element isolation portion. The lowest part of the bottom of the trench is lower than the surface of the semiconductor substrate and a sidewall spacer is formed in the side portion of the trench to cover the side surface of the insulating layer. As the result, even when the plug is formed in a deviated position, a disadvantage of conducting the semiconductor layer with the semiconductor substrate can be suppressed.Type: GrantFiled: October 8, 2018Date of Patent: October 20, 2020Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Nobuo Tsuboi
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Publication number: 20190393248Abstract: A semiconductor device includes an SOI substrate having an active region and an element isolation region adjacent to the active region, and including a support substrate, an insulating layer formed on the support substrate, and a semiconductor layer formed on the insulating layer, a trench formed in the element isolation region, and penetrating the semiconductor layer and the insulating layer so as to reach the support substrate, an element isolation insulating film embedded in the trench, the element isolation insulating film being made of silicon oxide film, a gate electrode formed on the semiconductor layer in the active region via a gate insulating film, a sidewall film formed on both sides of the gate electrode in cross-section view, the sidewall film being comprised of a first film made of silicon oxide film, and a second film made of silicon nitride film.Type: ApplicationFiled: September 9, 2019Publication date: December 26, 2019Inventor: Nobuo TSUBOI
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Patent number: 10340291Abstract: Reliability of a semiconductor device is improved. A p-type MISFET of a thin film SOI type is formed in an SOI substrate including a semiconductor substrate, an insulating layer on the semiconductor substrate, and a semiconductor layer on the insulating layer, and n+-type semiconductor regions which are source and drain region of the p-type MISFET are formed in the semiconductor layer and an epitaxial layer on the semiconductor layer. A semiconductor layer is formed via the insulating layer below the p-type MISFET formed in the n-type well region of the semiconductor substrate. In an n-type tap region which is a power supply region of the n-type well region, a silicide layer is formed on a main surface of the n-type well region without interposing the epitaxial layer therebetween.Type: GrantFiled: September 30, 2017Date of Patent: July 2, 2019Assignee: Renesas Electronics CorporationInventors: Nobuo Tsuboi, Yoshiki Yamamoto
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Publication number: 20190181157Abstract: There is provided with the following semiconductor device to improve its reliability. In a SOI substrate including a semiconductor substrate, an insulating layer, and a semiconductor layer, a diffusion region is formed in the semiconductor layer and a plug electrically connected to the diffusion region is formed on the diffusion region. An element isolation portion is formed within the semiconductor substrate and a trench is formed in the element isolation portion. The lowest part of the bottom of the trench is lower than the surface of the semiconductor substrate and a sidewall spacer is formed in the side portion of the trench to cover the side surface of the insulating layer. As the result, even when the plug is formed in a deviated position, a disadvantage of conducting the semiconductor layer with the semiconductor substrate can be suppressed.Type: ApplicationFiled: October 8, 2018Publication date: June 13, 2019Inventor: Nobuo TSUBOI
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Patent number: 10043813Abstract: A semiconductor device can be reduced in size. The semiconductor device has a first conductivity type p type well layer extending in the X direction of the main surface of a semiconductor substrate; a reference potential wire coupled with the p type well layer, and extending in the X direction; first and second active regions arranged on the opposite sides of the reference potential wire in the Y direction; and a gate electrode layer extending in the Y direction in such a manner as to cross with the first and second active regions . Then, the gate electrode layer has a first gate electrode of a second conductivity type at the crossing part with the first active region, a second gate electrode of the second conductivity type at the crossing part with the second active region, and a non-doped electrode between the first gate electrode and the second gate electrode.Type: GrantFiled: August 21, 2017Date of Patent: August 7, 2018Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Nobuo Tsuboi
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Publication number: 20180138204Abstract: Reliability of a semiconductor device is improved. A p-type MISFET of a thin film SOI type is formed in an SOI substrate including a semiconductor substrate, an insulating layer on the semiconductor substrate, and a semiconductor layer on the insulating layer, and n+-type semiconductor regions which are source and drain region of the p-type MISFET are formed in the semiconductor layer and an epitaxial layer on the semiconductor layer. A semiconductor layer is formed via the insulating layer below the p-type MISFET formed in the n-type well region of the semiconductor substrate. In an n-type tap region which is a power supply region of the n-type well region, a silicide layer is formed on a main surface of the n-type well region without interposing the epitaxial layer therebetween.Type: ApplicationFiled: September 30, 2017Publication date: May 17, 2018Inventors: Nobuo TSUBOI, Yoshiki YAMAMOTO
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Publication number: 20170373072Abstract: A semiconductor device can be reduced in size. The semiconductor device has a first conductivity type p type well layer extending in the X direction of the main surface of a semiconductor substrate; a reference potential wire coupled with the p type well layer, and extending in the X direction; first and second active regions arranged on the opposite sides of the reference potential wire in the Y direction; and a gate electrode layer extending in the Y direction in such a manner as to cross with the first and second active regions . Then, the gate electrode layer has a first gate electrode of a second conductivity type at the crossing part with the first active region, a second gate electrode of the second conductivity type at the crossing part with the second active region, and a non-doped electrode between the first gate electrode and the second gate electrode.Type: ApplicationFiled: August 21, 2017Publication date: December 28, 2017Inventor: Nobuo TSUBOI
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Publication number: 20170345750Abstract: Characteristics of a semiconductor device are improved. The semiconductor device is configured to include an SOI substrate including an active region and an element isolation region (element isolation insulating film), a gate electrode formed in the active region via a gate insulating film, and a dummy gate electrode formed in the element isolation region. A dummy sidewall film is formed on both sides of the dummy gate electrode, and is arranged to match or overlap a boundary between the active region and the element isolation region (element isolation insulating film). According to such a configuration, a plug can be prevented from deeply reaching, for example, an insulating layer and a support substrate even when a contact hole is formed to be shifted.Type: ApplicationFiled: May 1, 2017Publication date: November 30, 2017Inventor: Nobuo TSUBOI
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Patent number: 9741725Abstract: A semiconductor device can be reduced in size. The semiconductor device has a first conductivity type p type well layer extending in the X direction of the main surface of a semiconductor substrate; a reference potential wire coupled with the p type well layer, and extending in the X direction; first and second active regions arranged on the opposite sides of the reference potential wire in the Y direction; and a gate electrode layer extending in the Y direction in such a manner as to cross with the first and second active regions. Then, the gate electrode layer has a first gate electrode of a second conductivity type at the crossing part with the first active region, a second gate electrode of the second conductivity type at the crossing part with the second active region, and a non-doped electrode between the first gate electrode and the second gate electrode.Type: GrantFiled: May 17, 2016Date of Patent: August 22, 2017Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Nobuo Tsuboi
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Publication number: 20170012048Abstract: A semiconductor device can be reduced in size. The semiconductor device has a first conductivity type p type well layer extending in the X direction of the main surface of a semiconductor substrate; a reference potential wire coupled with the p type well layer, and extending in the X direction; first and second active regions arranged on the opposite sides of the reference potential wire in the Y direction; and a gate electrode layer extending in the Y direction in such a manner as to cross with the first and second active regions. Then, the gate electrode layer has a first gate electrode of a second conductivity type at the crossing part with the first active region, a second gate electrode of the second conductivity type at the crossing part with the second active region, and a non-doped electrode between the first gate electrode and the second gate electrode.Type: ApplicationFiled: May 17, 2016Publication date: January 12, 2017Inventor: Nobuo TSUBOI
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Publication number: 20160188787Abstract: A solid-state imaging device includes pixels respectively having photoelectric conversion units and arranged in matrix in basic pattern units, and an optical member arranged on the incidence side of incident light than the pixels and having constituent elements respectively corresponding to the pixels. The pixels include first, second and third wavelength range light pixels. Each basic pattern is comprised of a combined arrangement pattern of the wavelength range light pixels. Misregistration constituent elements with the occurrence of misregistration exist in the constituent elements. The misregistration increases toward the misregistration constituent elements separated from a center position of a pixel array of the pixels.Type: ApplicationFiled: March 8, 2016Publication date: June 30, 2016Inventors: Hiroyuki MOMONO, Nobuo TSUBOI
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Patent number: 9373654Abstract: A solid-state imaging device includes pixels respectively having photoelectric conversion units and arranged in matrix in basic pattern units, and an optical member arranged on the incidence side of incident light than the pixels and having constituent elements respectively corresponding to the pixels. The pixels include first, second and third wavelength range light pixels. Each basic pattern is comprised of a combined arrangement pattern of the wavelength range light pixels. Misregistration constituent elements with the occurrence of misregistration exist in the constituent elements. The misregistration increases toward the misregistration constituent elements separated from a center position of a pixel array of the pixels.Type: GrantFiled: October 30, 2014Date of Patent: June 21, 2016Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Hiroyuki Momono, Nobuo Tsuboi
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Patent number: 9230969Abstract: A semiconductor device in which wirings are formed adequately and electrical couplings are made properly in an SRAM memory cell. In the SRAM memory cell of the semiconductor device, a via to be electrically coupled to a third wiring as a word line is directly coupled to a contact plug electrically coupled to the gate wiring part of an access transistor. Also, another via to be electrically coupled to the third wiring as the word line is directly coupled to a contact plug electrically coupled to the gate wiring part of another access transistor.Type: GrantFiled: March 30, 2015Date of Patent: January 5, 2016Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Nobuo Tsuboi
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Publication number: 20150206889Abstract: A semiconductor device in which wirings are formed adequately and electrical couplings are made properly in an SRAM memory cell. In the SRAM memory cell of the semiconductor device, a via to be electrically coupled to a third wiring as a word line is directly coupled to a contact plug electrically coupled to the gate wiring part of an access transistor. Also, another via to be electrically coupled to the third wiring as the word line is directly coupled to a contact plug electrically coupled to the gate wiring part of another access transistor.Type: ApplicationFiled: March 30, 2015Publication date: July 23, 2015Inventor: Nobuo TSUBOI
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Publication number: 20150123229Abstract: A solid-state imaging device includes pixels respectively having photoelectric conversion units and arranged in matrix in basic pattern units, and an optical member arranged on the incidence side of incident light than the pixels and having constituent elements respectively corresponding to the pixels. The pixels include first, second and third wavelength range light pixels. Each basic pattern is comprised of a combined arrangement pattern of the wavelength range light pixels. Misregistration constituent elements with the occurrence of misregistration exist in the constituent elements. The misregistration increases toward the misregistration constituent elements separated from a center position of a pixel array of the pixels.Type: ApplicationFiled: October 30, 2014Publication date: May 7, 2015Inventors: Hiroyuki MOMONO, Nobuo TSUBOI
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Patent number: 9000503Abstract: A semiconductor device in which wirings are formed adequately and electrical couplings are made properly in an SRAM memory cell. In the SRAM memory cell of the semiconductor device, a via to be electrically coupled to a third wiring as a word line is directly coupled to a contact plug electrically coupled to the gate wiring part of an access transistor. Also, another via to be electrically coupled to the third wiring as the word line is directly coupled to a contact plug electrically coupled to the gate wiring part of another access transistor.Type: GrantFiled: May 15, 2012Date of Patent: April 7, 2015Assignee: Renesas Electronics CorporationInventor: Nobuo Tsuboi
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Patent number: 8350272Abstract: A semiconductor device which is designed based on RDR, suppresses the occurrence of a trouble at the boundary between an active region and a power wire and therearound and is small in size and highly integrated. The semiconductor device includes a first conductive impurity region for functional elements which is formed over the main surface of a semiconductor substrate and a second conductive impurity region for power potential to which power potential is applied in at least one standard cell. It also includes insulating layers which are formed over the main surface of the semiconductor substrate and have throughholes reaching the main surface of the semiconductor substrate, and a conductive layer for contact formed in the throughholes of the insulating layers.Type: GrantFiled: April 14, 2011Date of Patent: January 8, 2013Assignee: Renesas Electronics CorporationInventors: Nobuo Tsuboi, Masakazu Okada