Patents by Inventor Noburo Matsuda

Noburo Matsuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Vertical MOSFET having trench covered with multilayer gate film
    Patent number: 5321289
    Abstract: A vertical MOSFET includes a trench whose inner surface is covered with an insulating layer having a multilayer structure. In order to reduce a change in a gate threshold voltage, and equivalent silicon dioxide thickness of the gate insulating layer and a radius of curvature of an upper corner of the trench are provided such that a dielectric breakdown electric field strength of the gate insulating layer at the upper corner is in the range of 2.5 MV/cm to 5.0 MV/cm.
    Type: Grant
    Filed: October 21, 1993
    Date of Patent: June 14, 1994
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshiro Baba, Satoshi Yanagiya, Noburo Matsuda, Shunichi Hiraki