Patents by Inventor Nobushi Matsuura
Nobushi Matsuura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230317181Abstract: A semiconductor storage device of embodiments includes a block constituted with a plurality of strings each including a plurality of memory cell transistors, a plurality of word lines, a bit line, a source line, and a control circuit configured to perform erase operation on the plurality of memory cell transistors, and the control circuit changes setting of first erase-verify operation included in the erase operation for an open block including a memory cell transistor having an erase level and setting of second erase-verify operation included in erase operation for a closed block not including a memory cell transistor having an erase block.Type: ApplicationFiled: September 2, 2022Publication date: October 5, 2023Applicant: Kioxia CorporationInventors: Kenro KIKUCHI, Masahiko IGA, Nobushi MATSUURA
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Publication number: 20230307060Abstract: A semiconductor memory device performs a write operation and an erase operation. The write operation includes a first program operation that applies a first program voltage to a first conductive layer. The first program voltage increases by a first offset voltage together with an increase in an execution count of a first write loop. An erase operation includes a program voltage control operation and an erase voltage supply operation that applies an erase voltage to a first wiring. The program voltage control operation includes a second program operation that applies a second program voltage to a third conductive layer. The second program voltage increases by a second offset voltage together with an increase in a number of times of execution of a second write loop. A magnitude of the first program voltage is adjusted according to a magnitude of the second program voltage.Type: ApplicationFiled: September 8, 2022Publication date: September 28, 2023Applicant: Kioxia CorporationInventors: Masahiko IGA, Kenro KIKUCHI, Nobushi MATSUURA
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Patent number: 11309322Abstract: A semiconductor memory device according to an embodiment includes a semiconductor substrate; a laminated body formed by laminating a plurality of electrode layers on the semiconductor substrate; a memory film provided in the laminated body and including a first block insulation film disposed in a direction perpendicular to the electrode layer, a charge storage film facing the first block insulation film, a tunnel insulation film facing the charge storage film, and a channel film facing the tunnel insulation film; and a barrier layer provided at at least one of interface between the plurality of electrode layers and the memory film and an interface in the memory film and mainly composed of carbon.Type: GrantFiled: September 12, 2019Date of Patent: April 19, 2022Assignee: KIOXIA CORPORATIONInventors: Ryota Fujitsuka, Kenta Yamada, Takanori Yamanaka, Takayuki Okada, Hirokazu Ishigaki, Hiroki Kishi, Nobushi Matsuura, Takashi Yamane, Ryota Suzuki
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Publication number: 20200303393Abstract: A semiconductor memory device according to an embodiment includes a semiconductor substrate; a laminated body formed by laminating a plurality of electrode layers on the semiconductor substrate; a memory film provided in the laminated body and including a first block insulation film disposed in a direction perpendicular to the electrode layer, a charge storage film facing the first block insulation film, a tunnel insulation film facing the charge storage film, and a channel film facing the tunnel insulation film; and a barrier layer provided at at least one of interface between the plurality of electrode layers and the memory film and an interface in the memory film and mainly composed of carbon.Type: ApplicationFiled: September 12, 2019Publication date: September 24, 2020Applicant: Toshiba Memory CorporationInventors: Ryota Fujitsuka, Kenta Yamada, Takanori Yamanaka, Takayuki Okada, Hirokazu Ishigaki, Hiroki Kishi, Nobushi Matsuura, Takashi Yamane, Ryota Suzuki
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Patent number: 9672926Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and a control circuit configured to repeat a program operation and a verify operation. The control circuit performs a first verify operation of sensing whether threshold voltages of selected memory cells are greater than or equal to a first threshold voltage, and a second verify operation of sensing whether the threshold voltages of the selected memory cells are greater than or equal to a second threshold voltage (first threshold voltage<second threshold voltage), and the control circuit changes a charge voltage for the bit lines between the first verify operation and the second verify operation.Type: GrantFiled: August 29, 2013Date of Patent: June 6, 2017Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Yasuhiro Shiino, Nobushi Matsuura, Masashi Yoshida, Eietsu Takahashi
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Patent number: 9153326Abstract: The disclosure describes a semiconductor memory device including a memory cell array and a control circuit. The memory cell array comprises a plurality of memory cells that each include a control gate and a charge accumulation layer and that each are configured to have a threshold set to be included in any of a plurality of threshold distributions, the memory cell being connected between a bit line and a source line. The control circuit, in at least one of a write verify operation and a read operation on a selected memory cell, applies to the control gate a control gate voltage to determine the threshold of the selected memory cell, the control gate voltage having a plurality of values respectively corresponded to the plurality of threshold distributions, and sets a voltage between the bit line and the source line based on the control gate voltage.Type: GrantFiled: September 4, 2013Date of Patent: October 6, 2015Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Masashi Yoshida, Eietsu Takahashi, Yasuhiro Shiino, Nobushi Matsuura
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Publication number: 20140340964Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and a control circuit configured to repeat a program operation and a verify operation. The control circuit performs a first verify operation of sensing whether threshold voltages of selected memory cells are greater than or equal to a first threshold voltage, and a second verify operation of sensing whether the threshold voltages of the selected memory cells are greater than or equal to a second threshold voltage (first threshold voltage<second threshold voltage), and the control circuit changes a charge voltage for the bit lines between the first verify operation and the second verify operation.Type: ApplicationFiled: August 29, 2013Publication date: November 20, 2014Inventors: Yasuhiro SHIINO, Nobushi MATSUURA, Masashi YOSHIDA, Eietsu TAKAHASHI
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Publication number: 20140241058Abstract: According to an embodiment, a semiconductor memory device includes a memory cell array and a control circuit. The memory cell array comprises a plurality of memory cells that each include a control gate and a charge accumulation layer and that each are configured to have a threshold set to be included in any of a plurality of threshold distributions, the memory cell being connected between a bit line and a source line. The control circuit, in at least one of a write verify operation and a read operation on a selected memory cell, applies to the control gate a control gate voltage to determine the threshold of the selected memory cell, the control gate voltage having a plurality of values respectively corresponded to the plurality of threshold distributions, and sets a voltage between the bit line and the source line based on the control gate voltage.Type: ApplicationFiled: September 4, 2013Publication date: August 28, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Masashi Yoshida, Eietsu Takahashi, Yasuhiro Shiino, Nobushi Matsuura