Abstract: A semiconductor apparatus includes a memory array that is disposed such that bit line pairs are arranged in a plurality of columns in a column direction and the bit line pairs are connected to one data latch circuit, in which a plurality of memory cells are connected to the bit line pair, a precharge circuit that blocks precharge of a bit line pair that is selected by a column address signal among the plurality of bit line pairs and precharges the bit line pairs other than the bit line pair selected by the column address signal, and a data latch circuit that outputs read data from the memory array based on potentials of a first bit line and a second bit line, in which the first bit line constitutes a first bit line pair, and the second bit line pair constitutes a second bit line pair.