Patents by Inventor Nobusuke Yamamoto

Nobusuke Yamamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240149260
    Abstract: The exhaust gas purification device includes a substrate, a first catalyst layer, and a second catalyst layer. The substrate includes an upstream end and a downstream end. The first catalyst layer contains first catalyst particles and lies on the substrate across a first region extending between the upstream end and a first position. The first position is at a first distance from the upstream end toward the downstream end. The second catalyst layer contains second catalyst particles and lies on the first catalyst layer across the first region. The second catalyst layer is provided with pores. Pore connectivity of the second catalyst layer is 5% to 35%. A mean value of areas of the pores of the second catalyst layer in a cross-sectional backscattered electron image of the second catalyst layer may be 0.7 ?m2 to 9.0 ?m2.
    Type: Application
    Filed: November 7, 2023
    Publication date: May 9, 2024
    Applicants: TOYOTA JIDOSHA KABUSHIKI KAISHA, KABUSHIKI KAISHA TOYOTA CHUO KENKYUSHO, CATALER CORPORATION
    Inventors: Nobusuke KABASHIMA, Toshio YAMAMOTO, Miho HATANAKA, Tetsuya SHINOZAKI
  • Patent number: 6908777
    Abstract: A method of controlling characteristics of a compound semiconductor device, whereby the compound semiconductor device is formed so as to include a plurality of resistors having the same ratio of a difference between a surface area of a corresponding resistivity region and the combined overlapping surface area of a corresponding pair of electrodes to the combined overlapping surface area of the corresponding pair of electrodes. In this manner, a resistivity of a resistor is precisely controlled.
    Type: Grant
    Filed: November 21, 2002
    Date of Patent: June 21, 2005
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Nobusuke Yamamoto
  • Publication number: 20030075727
    Abstract: A compound semiconductor device is formed having a plurality of FETs exhibiting the same electrode ratio of a difference between a surface area the active region and the combined overlapping surface area of the source and drain ohmic electrodes to the combined overlapping surface area of the source and drain ohmic electrodes. As such, precise control of a threshold voltage of the FETs is achieved. The compound semiconductor device is also formed so as to include a plurality of resistors having the same ratio of a difference between a surface area of the resistivity region and the combined overlapping surface area of the pair electrodes to the combined overlapping surface area of the pair electrodes. In this manner, a resistivity of the resistor is precisely controlled.
    Type: Application
    Filed: November 21, 2002
    Publication date: April 24, 2003
    Inventor: Nobusuke Yamamoto
  • Patent number: 6537865
    Abstract: A semiconductor device fabrication process includes forming a Schottky layer, a cap layer covering the surface of the Schottky layer, and a Schottky electrode of a two-level structure having a lower portion that penetrates through the cap layer and reaches the Schottky layer, and having an upper portion larger than the lower portion in cross-sectional area and that overlies the cap layer. With this construction, surface defects are unlikely to occur, so that a highly reliable semiconductor device can be fabricated.
    Type: Grant
    Filed: August 16, 2001
    Date of Patent: March 25, 2003
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Kazuyuki Inokuchi, Seiichi Takahashi, Shinichi Hoshi, Tadashi Saito, Nobusuke Yamamoto, Yuko Itoh, Nobumasa Higemoto
  • Patent number: 6504185
    Abstract: A compound semiconductor device is formed having a plurality of FETs exhibiting the same electrode ratio of a difference between a surface area of the active region and the combined overlapping surface area of the source and drain ohmic electrodes to the combined overlapping surface area of the source and drain ohmic electrodes. As such, precise control of a threshold voltage of the FETs is achieved. The compound semiconductor device is also formed so as to include a plurality of resistors having the same ratio of a difference between a surface area of the resistivity region and the combined overlapping surface area of the pair electrodes to the combined overlapping surface area of the pair electrodes. In this manner, a resistivity of the resistor is precisely controlled.
    Type: Grant
    Filed: June 5, 2001
    Date of Patent: January 7, 2003
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Nobusuke Yamamoto
  • Publication number: 20020024057
    Abstract: A semiconductor device according to the invention comprises a Schottky layer, a cap layer covering the surface of the Schottky layer, and a Schottky electrode of a two-level structure, having an under structure penetrating through the cap layer and reaching the Schottky layer, and an upper structure larger than the under structure in a cross-sectional area and overlying the cap layer. With such a construction as described, surface defect is unlikely to occur, and therefore, a highly reliable semiconductor device can be fabricated.
    Type: Application
    Filed: August 16, 2001
    Publication date: February 28, 2002
    Inventors: Kazuyuki Inokuchi, Seiichi Takahashi, Shinichi Hoshi, Tadashi Saito, Nobusuke Yamamoto, Yuko Itoh, Nobumasa Higemoto
  • Publication number: 20010028070
    Abstract: A compound semiconductor device is formed having a plurality of FETs exhibiting the same electrode ratio of a difference between a surface area of the active region and the combined overlapping surface area of the source and drain ohmic electrodes to the combined overlapping race area of the source and drain ohmic electrodes. As such, precise control of a threshold voltage of the FETs is achieved The compound semiconductor device is also formed, so as to include a plurality of resistors having the same ratio of a difference between a surface area of the resistivity region and the combined overlapping surface area of the pair electrodes to the combined overlapping surface area of the pair electrodes. In this manner, a resistivity of the resistor is precisely controlled.
    Type: Application
    Filed: June 5, 2001
    Publication date: October 11, 2001
    Inventor: Nobusuke Yamamoto
  • Patent number: 6294801
    Abstract: A semiconductor device includes a Schottky layer, a cap layer covering the surface of the Schottky layer, and a Schottky electrode of a two-level structure. The Schottky electrode has a lower portion that penetrates through the cap layer and reaches the Schottky layer, and has an upper portion larger than the lower portion in cross-sectional area and that overlies the cap layer. With this construction, surface defects are unlikely to occur, so that a highly reliable semiconductor device can be fabricated.
    Type: Grant
    Filed: April 22, 1999
    Date of Patent: September 25, 2001
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Kazuyuki Inokuchi, Seiichi Takahashi, Shinichi Hoshi, Tadashi Saito, Nobusuke Yamamoto, Yuko Itoh, Nobumasa Higemoto
  • Patent number: 6265728
    Abstract: A compound semiconductor device is formed having a plurality of FETs exhibiting the same electrode ratio of a difference between a surface area of the active region and the combined overlapping surface area of the source and drain ohmic electrodes to the combined overlapping surface area of the source and drain ohmic electrodes. As such, precise control of a threshold voltage of the FETs is achieved. The compound semiconductor device is also formed so as to include a plurality of resistors having the same ratio of a difference between a surface area of the resistivity region and the combined overlapping surface area of the pair electrodes to the combined overlapping surface area of the pair electrodes. In this manner, a resistivity of the resistor is precisely controlled.
    Type: Grant
    Filed: March 19, 1998
    Date of Patent: July 24, 2001
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Nobusuke Yamamoto
  • Patent number: 4838945
    Abstract: A thermoplastic resin composition for cleaning a shaping apparatus such as an extrude by a simple operation, comprising 2-30% by weight of a sodium salt of sulfonic acid, 0.5-10% by weight of a water-repellent compound and a thermoplastic resin and as an optional component, finely ground inorganic compound having a particle size of 0.005 to 10 .mu.m.
    Type: Grant
    Filed: February 20, 1987
    Date of Patent: June 13, 1989
    Assignee: Chisso Corporation
    Inventors: Hiroyuki Fujii, Takamichi Kudo, Haruhiko Furukawa, Nobusuke Yamamoto