Patents by Inventor Nobutaka Imanishi
Nobutaka Imanishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7742337Abstract: A semiconductor memory is achieved which allows a reduction in the area of a memory array block without reducing the gate widths of floating gates. A plurality of select gates extend in straight lines in the X direction. Between the upper- and lower-side select gates, two rows' worth of floating gates are arranged. The plurality of floating gates are placed in a staggered arrangement (in other words, in a zigzag pattern). That is, looking at one floating gate in a specific column and another floating gate in a column adjacent to that specific column, those floating gates deviate from each other in the Y direction.Type: GrantFiled: November 6, 2008Date of Patent: June 22, 2010Assignee: Renesas Technology Corp.Inventors: Yutaka Takikawa, Koichi Kawauchi, Satoko Kamakura, Kazuo Nomura, Kazuyuki Kawamoto, Nobutaka Imanishi
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Publication number: 20090059665Abstract: A semiconductor memory is achieved which allows a reduction in the area of a memory array block without reducing the gate widths of floating gates. A plurality of select gates extend in straight lines in the X direction. Between the upper- and lower-side select gates, two rows' worth of floating gates are arranged. The plurality of floating gates are placed in a staggered arrangement (in other words, in a zigzag pattern). That is, looking at one floating gate in a specific column and another floating gate in a column adjacent to that specific column, those floating gates deviate from each other in the Y direction.Type: ApplicationFiled: November 6, 2008Publication date: March 5, 2009Applicant: Renesas Technology Corp.Inventors: Yutaka Takikawa, Koichi Kawauchi, Satoko Kamakura, Kazuo Nomura, Kazuyuki Kawamoto, Nobutaka Imanishi
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Patent number: 7486556Abstract: A semiconductor memory is achieved which allows a reduction in the area of a memory array block without reducing the gate widths of floating gates. A plurality of select gates extend in straight lines in the X direction. Between the upper- and lower-side select gates, two rows' worth of floating gates are arranged. The plurality of floating gates are placed in a staggered arrangement (in other words, in a zigzag pattern). That is, looking at one floating gate in a specific column and another floating gate in a column adjacent to that specific column, those floating gates deviate from each other in the Y direction.Type: GrantFiled: August 6, 2007Date of Patent: February 3, 2009Assignee: Renesas Technology Corp.Inventors: Yutaka Takikawa, Koichi Kawauchi, Satoko Kamakura, Kazuo Nomura, Kazuyuki Kawamoto, Nobutaka Imanishi
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Publication number: 20080175051Abstract: A semiconductor memory is achieved which allows a reduction in the area of a memory array block without reducing the gate widths of floating gates. A plurality of select gates extend in straight lines in the X direction. Between the upper- and lower-side select gates, two rows' worth of floating gates are arranged. The plurality of floating gates are placed in a staggered arrangement (in other words, in a zigzag pattern). That is, looking at one floating gate in a specific column and another floating gate in a column adjacent to that specific column, those floating gates deviate from each other in the Y direction.Type: ApplicationFiled: August 6, 2007Publication date: July 24, 2008Inventors: Yutaka Takikawa, Koichi Kawauchi, Satoko Kamakura, Kazuo Nomura, Kazuyuki Kawamoto, Nobutaka Imanishi
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Patent number: 7400530Abstract: A semiconductor memory is achieved which allows a reduction in the area of a memory array block without reducing the gate widths of floating gates. A plurality of select gates extend in straight lines in the X direction. Between the upper- and lower-side select gates, two rows' worth of floating gates are arranged. The plurality of floating gates are placed in a staggered arrangement (in other words, in a zigzag pattern). That is, looking at one floating gate in a specific column and another floating gate in a column adjacent to that specific column, those floating gates deviate from each other in the Y direction.Type: GrantFiled: August 6, 2007Date of Patent: July 15, 2008Assignee: Renesas Technology Corp.Inventors: Yutaka Takikawa, Koichi Kawauchi, Satoko Kamakura, Kazuo Nomura, Kazuyuki Kawamoto, Nobutaka Imanishi
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Publication number: 20070285991Abstract: A semiconductor memory is achieved which allows a reduction in the area of a memory array block without reducing the gate widths of floating gates. A plurality of select gates extend in straight lines in the X direction. Between the upper- and lower-side select gates, two rows' worth of floating gates are arranged. The plurality of floating gates are placed in a staggered arrangement (in other words, in a zigzag pattern). That is, looking at one floating gate in a specific column and another floating gate in a column adjacent to that specific column, those floating gates deviate from each other in the Y direction.Type: ApplicationFiled: August 6, 2007Publication date: December 13, 2007Inventors: Yutaka Takikawa, Koichi Kawauchi, Satoko Kamakura, Kazuo Nomura, Kazuyuki Kawamoto, Nobutaka Imanishi
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Patent number: 7307889Abstract: A semiconductor memory is achieved which allows a reduction in the area of a memory array block without reducing the gate widths of floating gates. A plurality of select gates extend in straight lines in the X direction. Between the upper- and lower-side select gates, two rows' worth of floating gates are arranged. The plurality of floating gates are placed in a staggered arrangement (in other words, in a zigzag pattern). That is, looking at one floating gate in a specific column and another floating gate in a column adjacent to that specific column, those floating gates deviate from each other in the Y direction.Type: GrantFiled: April 5, 2005Date of Patent: December 11, 2007Assignee: Renesas Technology Corp.Inventors: Yutaka Takikawa, Koichi Kawauchi, Satoko Kamakura, Kazuo Nomura, Kazuyuki Kawamoto, Nobutaka Imanishi
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Publication number: 20050226053Abstract: A semiconductor memory is achieved which allows a reduction in the area of a memory array block without reducing the gate widths of floating gates. A plurality of select gates extend in straight lines in the X direction. Between the upper- and lower-side select gates, two rows' worth of floating gates are arranged. The plurality of floating gates are placed in a staggered arrangement (in other words, in a zigzag pattern). That is, looking at one floating gate in a specific column and another floating gate in a column adjacent to that specific column, those floating gates deviate from each other in the Y direction.Type: ApplicationFiled: April 5, 2005Publication date: October 13, 2005Applicant: Renesas Technology Corp.Inventors: Yutaka Takikawa, Koichi Kawauchi, Satoko Kamakura, Kazuo Nomura, Kazuyuki Kawamoto, Nobutaka Imanishi