Patents by Inventor Nobutaka ISHIZUKA

Nobutaka ISHIZUKA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10566420
    Abstract: A semiconductor device of an embodiment includes an overvoltage protection diode in which an N-type semiconductor layer and a P-type semiconductor layer, formed on an insulating film in a voltage supporting region, are alternately disposed adjacently to each other. The overvoltage protection diode is disposed at a corner portion on the upper face of the insulating film, and extends from the corner portion to the center portion of the semiconductor substrate.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: February 18, 2020
    Assignee: Shindengen Electric Manufacturing Co., Ltd.
    Inventors: Ryohei Kotani, Toshiki Matsubara, Nobutaka Ishizuka, Masato Mikawa, Hiroshi Oshino
  • Patent number: 10424578
    Abstract: A semiconductor device of an embodiment includes a conductive semiconductor substrate, an insulating film formed on the semiconductor substrate, an overvoltage protection diode configured to be formed on the insulating film and to include an n-type semiconductor layer and a p-type semiconductor layer alternately arranged adjacent to each other, and an insulating film that covers the overvoltage protection diode. The concentration of the p-type impurities in the p-type semiconductor layer is lower than the concentration of the n-type impurities in the n-type semiconductor layer. The concentration peak of the p-type impurities is disposed in a non-boundary region between a boundary region and a boundary region.
    Type: Grant
    Filed: September 13, 2016
    Date of Patent: September 24, 2019
    Assignee: Shindengen Electric Manufacturing Co., Ltd.
    Inventors: Ryohei Kotani, Toshiki Matsubara, Nobutaka Ishizuka, Masato Mikawa, Hiroshi Oshino
  • Patent number: 10366976
    Abstract: A semiconductor switch SW that includes a collector electrode C, an emitter electrode E and a gate electrode G, a Zener diode 5A configured to include one end electrically connected to the collector electrode C, the other end electrically connected to the gate electrode G, and n-type semiconductor layers and p-type semiconductor layers alternately arranged adjacent to each other, a Zener diode 5B configured to include one end electrically connected to the gate electrode G, the other end electrically connected to the emitter electrode E, and n-type semiconductor layers and p-type semiconductor layers alternately arranged adjacent to each other, are provided. The Zener diode 5A and the Zener diode 5B are configured so as not to allow the voltage of the gate electrode G to be increased to an on-threshold voltage of the semiconductor switch SW in the reverse bias application state.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: July 30, 2019
    Assignee: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.
    Inventors: Ryohei Kotani, Toshiki Matsubara, Nobutaka Ishizuka, Masato Mikawa, Hiroshi Oshino
  • Patent number: 10361184
    Abstract: A semiconductor device according to an embodiment includes: an insulating film formed on a voltage supporting region B; an overvoltage protection diode that includes an n-type semiconductor layer and a p-type semiconductor layer; conductor portions that are formed on the insulating film and are electrically connected to the overvoltage protection diode; and a high-potential portion arranged above the overvoltage protection diode via an insulating film. The p-type impurity concentration of the p-type semiconductor layer is lower than the n-type impurity concentration of the n-type semiconductor layer. In the reverse bias application state, the high-potential portion has a higher potential than a potential of the potential of the p-type semiconductor layer disposed directly under the high-potential portion.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: July 23, 2019
    Assignee: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.
    Inventors: Ryohei Kotani, Toshiki Matsubara, Nobutaka Ishizuka, Masato Mikawa, Hiroshi Oshino
  • Publication number: 20190148354
    Abstract: A semiconductor switch SW that includes a collector electrode C, an emitter electrode E and a gate electrode G, a Zener diode 5A configured to include one end electrically connected to the collector electrode C, the other end electrically connected to the gate electrode G, and n-type semiconductor layers and p-type semiconductor layers alternately arranged adjacent to each other, a Zener diode 5B configured to include one end electrically connected to the gate electrode G, the other end electrically connected to the emitter electrode E, and n-type semiconductor layers and p-type semiconductor layers alternately arranged adjacent to each other, are provided. The Zener diode 5A and the Zener diode 5B are configured so as not to allow the voltage of the gate electrode G to be increased to an on-threshold voltage of the semiconductor switch SW in the reverse bias application state.
    Type: Application
    Filed: December 22, 2016
    Publication date: May 16, 2019
    Applicant: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.
    Inventors: Ryohei KOTANI, Toshiki MATSUBARA, Nobutaka ISHIZUKA, Masato MIKAWA, Hiroshi OSHINO
  • Patent number: 10199483
    Abstract: In a semiconductor device according to an embodiment, ends of conductor portions are electrically connected to an overvoltage protection diode so that depletion occurs in a diffusion layer in a portion near an insulating film in a reverse bias application state, and/or ends of conductor portions are electrically connected to the overvoltage protection diode so that depletion occurs in a peripheral semiconductor region in a portion near the insulating film in the reverse bias application state.
    Type: Grant
    Filed: May 26, 2016
    Date of Patent: February 5, 2019
    Assignee: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.
    Inventors: Ryohei Kotani, Toshiki Matsubara, Nobutaka Ishizuka, Masato Mikawa, Hiroshi Oshino
  • Publication number: 20180331178
    Abstract: A semiconductor device of an embodiment includes an overvoltage protection diode in which an N-type semiconductor layer and a P-type semiconductor layer, formed on an insulating film in a voltage supporting region, are alternately disposed adjacently to each other. The overvoltage protection diode is disposed at a corner portion on the upper face of the insulating film, and extends from the corner portion to the center portion of the semiconductor substrate.
    Type: Application
    Filed: September 30, 2016
    Publication date: November 15, 2018
    Applicant: Shindengen Electric Manufacturing Co., Ltd.
    Inventors: Ryohei KOTANI, Toshiki MATSUBARA, Nobutaka ISHIZUKA, Masato MIKAWA, Hiroshi OSHINO
  • Publication number: 20180331092
    Abstract: A semiconductor device according to an embodiment includes: an insulating film formed on a voltage supporting region B; an overvoltage protection diode that includes an n-type semiconductor layer and a p-type semiconductor layer; conductor portions that are formed on the insulating film and are electrically connected to the overvoltage protection diode; and a high-potential portion arranged above the overvoltage protection diode via an insulating film. The p-type impurity concentration of the p-type semiconductor layer is lower than the n-type impurity concentration of the n-type semiconductor layer. In the reverse bias application state, the high-potential portion has a higher potential than a potential of the potential of the p-type semiconductor layer disposed directly under the high-potential portion.
    Type: Application
    Filed: September 30, 2016
    Publication date: November 15, 2018
    Applicant: Shindengen Electric Manufecturing Co., Ltd.
    Inventors: Ryohei KOTANI, Toshiki MATSUBARA, Nobutaka ISHIZUKA, Masato MIKAWA, Hiroshi OSHINO
  • Publication number: 20180294257
    Abstract: A semiconductor device of an embodiment includes a conductive semiconductor substrate, an insulating film formed on the semiconductor substrate, an overvoltage protection diode configured to be formed on the insulating film and to include an n-type semiconductor layer and a p-type semiconductor layer alternately arranged adjacent to each other, and an insulating film that covers the overvoltage protection diode. The concentration of the p-type impurities in the p-type semiconductor layer is lower than the concentration of the n-type impurities in the n-type semiconductor layer. The concentration peak of the p-type impurities is disposed in a non-boundary region between a boundary region and a boundary region.
    Type: Application
    Filed: September 13, 2016
    Publication date: October 11, 2018
    Applicant: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.
    Inventors: Ryohei Kotani, Toshiki Matsubara, Nobutaka Ishizuka, Masato Mikawa, Hiroshi Oshino
  • Publication number: 20180204935
    Abstract: In a semiconductor device according to an embodiment, ends of conductor portions are electrically connected to an overvoltage protection diode so that depletion occurs in a diffusion layer in a portion near an insulating film in a reverse bias application state, and/or ends of conductor portions are electrically connected to the overvoltage protection diode so that depletion occurs in a peripheral semiconductor region in a portion near the insulating film in the reverse bias application state.
    Type: Application
    Filed: May 26, 2016
    Publication date: July 19, 2018
    Applicant: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.
    Inventors: Ryohei KOTANI, Toshiki MATSUBARA, Nobutaka ISHIZUKA, Masato MIKAWA, Hiroshi OSHINO