Patents by Inventor Nobutaka Itagaki

Nobutaka Itagaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060125512
    Abstract: A method for inspecting an active-matrix-display-panel array substrate includes: a first step of applying a voltage V1 to the data terminal of a transistor while the transistor conducts, bringing the transistor into a non-conductive state, applying a voltage V1+?V to the data terminal, bringing the transistor into a conductive state, and measuring charge ?Q; a second step of applying a voltage V0 to the data terminal when the transistor does not conduct and the data terminal voltage is V3, and measuring a voltage Q1 flowing through the transistor when the transistor conducts; a third step of applying a voltage V0? to the data terminal when the transistor does not conduct and the data terminal voltage is V4, and measuring charge Q2 flowing when the transistor conducts; and a fourth step of determining a capacitance of the capacitor based on ?V, ?Q, V0, V0?, V3, V4, Q1, and Q2.
    Type: Application
    Filed: December 8, 2005
    Publication date: June 15, 2006
    Inventors: Nobutaka Itagaki, Hideyuki Norimatsu
  • Patent number: 7012445
    Abstract: A method for testing a TFT array that comprises one or a plurality of first pixels including capacitors connected to one terminal of pixel selection switches, one or a plurality of second pixels including capacitors connected to one terminal of pixel selection switches, and data lines connected to the other terminals of the pixel selection switches of the first pixels and the other terminals of the pixel selection switches of the second pixels, wherein the method for testing comprises a step for charging the capacitors of the first pixels to a first voltage, a step for charging the capacitors of the second pixels to a second voltage, a step for turning on both the pixel selection switches of the first pixels and the pixel selection switches of the second pixels, and a step for measuring either one or both of the voltage of a data line or the charge flowing through the data line.
    Type: Grant
    Filed: December 3, 2004
    Date of Patent: March 14, 2006
    Assignee: Agilent Technologies, Inc.
    Inventor: Nobutaka Itagaki
  • Publication number: 20050206404
    Abstract: A method for testing a TFT array that comprises one or a plurality of first pixels including capacitors connected to one terminal of pixel selection switches, one or a plurality of second pixels including capacitors connected to one terminal of pixel selection switches, and data lines connected to the other terminals of the pixel selection switches of the first pixels and the other terminals of the pixel selection switches of the second pixels, wherein the method for testing comprises a step for charging the capacitors of the first pixels to a first voltage, a step for charging the capacitors of the second pixels to a second voltage, a step for turning on both the pixel selection switches of the first pixels and the pixel selection switches of the second pixels, and a step for measuring either one or both of the voltage of a data line or the charge flowing through the data line.
    Type: Application
    Filed: December 3, 2004
    Publication date: September 22, 2005
    Inventor: Nobutaka Itagaki