Abstract: According to one embodiment, a semiconductor device includes: a clock generation circuit configured to receive a first clock signal and to generate a second clock signal from the first clock signal; a first phase adjustment circuit configured to generate a first control signal using the first clock signal and the second clock signal; and a second phase adjustment circuit configured to receive data and to add a first delay value based on the first control signal to the data.

Abstract: According to one embodiment, a semiconductor device includes: a clock generation circuit configured to receive a first clock signal and to generate a second clock signal from the first clock signal; a first phase adjustment circuit configured to generate a first control signal using the first clock signal and the second clock signal; and a second phase adjustment circuit configured to receive data and to add a first delay value based on the first control signal to the data.

Abstract: An electrostatic discharge (ESD) protection circuit includes first and second transistors connected in series between first and second power supply nodes. A third transistor of the ESD protection circuit turns the second transistor to OFF during normal operation. A fourth transistor of the ESD protection circuit turns the first transistor ON during ESD operation. During normal operation, a damping time constant circuit of the ESD protection circuit turns the fourth transistor OFF, and during ESD operation, turns the fourth transistor ON. A fifth transistor of the ESD protection circuit turns the second transistor ON during ESD operation. The first to fifth transistors each have a voltage resistance level that is lower than power supply voltage.

Abstract: A semiconductor integrated circuit having protection elements for protecting a MOSFET of a high accuracy analog circuit from plasma damage generated during a manufacture of the semiconductor integrated circuit is provided. The protection elements operate at a lower voltage of PN junction breakdown voltage so as to prevent transistors from degrading or having dielectric breakdown due to plasma damage. A differential amplifier includes first and second n-channel MOS transistors for constructing a differential input pair. A first protection element comprising a plurality of gate-drain connected MOS transistors coupled as a cascade is provided between the gate of the first n-channel MOS transistor and a first differential input terminal. A second protection element comprising a plurality of gate-drain connected MOS transistors coupled as a cascade is provided between the gate of the second n-channel MOS transistor and a second differential input terminal.

Abstract: A semiconductor integrated circuit device is disclosed, which comprises power supply system circuits, in which power supply terminals and/or ground terminals are separated from each other between the power supply system circuits, an electrostatic discharge protecting circuit, an internal circuit provided in each of the power supply system circuits, an internal signal transmitting line, a surge input detecting circuit, and at least one of an input protecting circuit which is provided at an input side of the internal circuit and which limits a voltage of a signal transmitted from the internal signal transmitting line, and an output logic setting circuit which is provided at an output side of the internal circuit and which sets a logic level of a signal outputted to the internal signal transmitting line to a low level when the surge input detecting circuit has detected a surge input.

Abstract: An output driving circuit has a first and second differential output nodes connected to a first and second external output terminals, respectively. A capacitance connection circuit is connected between the first and second differential output nodes. The capacitance connection circuit connects a capacitance between the first and second differential output nodes. The capacitance connection circuit then adjusts the value of the capacitance in accordance with a control signal.

Abstract: A semiconductor circuit system has first, second, and third external terminals electrically separated from each other. The first external terminal is configured to receive a first power supply voltage in a normal operation. A protection circuit section is provided in the circuit system and includes a rectifier to allow a surge current to pass therethrough. The rectifier has a current passage connected between a specific terminal connected to a protection target and the third external terminal. The protection circuit section further includes a first PMOS transistor configured to trigger the rectifier, based on a surge voltage inputted into the second external terminal. The first PMOS transistor has a current passage connected between the second external terminal and a base of the NPN transistor. The first PMOS transistor has a gate connected to the first external terminal.

Abstract: An electrostatic discharge protection circuit device is disclosed, which comprises a first electrostatic discharge protection circuit connected between a first external terminal and a first ground terminal, a second electrostatic discharge protection circuit connected between a second external terminal and a second ground terminal, the second electrostatic discharge protection circuit having substantially the same configuration as that of the first electrostatic discharge protection circuit, a trigger signal line which connects to each other output nodes of surge detection circuits of the first and second electrostatic discharge protection circuits, and transfers a surge detection output of the first or second electrostatic discharge protection circuit to the other electrostatic discharge protection circuit as a trigger signal, and a common discharge line connected directly to the first ground terminal, connected to the second ground terminal via a parallel circuit composed of a forward-connected parasitic di

Abstract: A semiconductor device having a protection circuit comprising an NPN type bipolar transistor having a collector and an emitter connected between an external connection terminal of the semiconductor device to be protected and a reference terminal, a PMOS transistor having a drain and source connected between the base and the collector of the NPN type bipolar transistor and configured to supply a base current to the base of the NPN type bipolar transistor, and a control circuit configured to supply the control signal to the gate of the PMOS transistor in response to a voltage emerging on the external connection terminal.

Abstract: An output driving circuit has a first and second differential output nodes connected to a first and second external output terminals, respectively. A capacitance connection circuit is connected between the first and second differential output nodes. The capacitance connection circuit connects a capacitance between the first and second differential output nodes. The capacitance connection circuit then adjusts the value of the capacitance in accordance with a control signal.

Abstract: A semiconductor integrated circuit device is disclosed, which comprises power supply system circuits, in which power supply terminals and/or ground terminals are separated from each other between the power supply system circuits, an electrostatic discharge protecting circuit, an internal circuit provided in each of the power supply system circuits, an internal signal transmitting line, a surge input detecting circuit, and at least one of an input protecting circuit which is provided at an input side of the internal circuit and which limits a voltage of a signal transmitted from the internal signal transmitting line, and an output logic setting circuit which is provided at an output side of the internal circuit and which sets a logic level of a signal outputted to the internal signal transmitting line to a low level when the surge input detecting circuit has detected a surge input.

Abstract: A semiconductor integrated circuit having protection elements for protecting a MOSFET of a high accuracy analog circuit from plasma damage generated during a manufacture of the semiconductor integrated circuit is provided. The protection elements operate at a lower voltage of PN junction breakdown voltage so as to prevent transistors from degrading or having dielectric breakdown due to plasma damage. A differential amplifier includes first and second n-channel MOS transistors for constructing a differential input pair. A first protection element comprising a plurality of gate-drain connected MOS transistors coupled as a cascade is provided between the gate of the first n-channel MOS transistor and a first differential input terminal. A second protection element comprising a plurality of gate-drain connected MOS transistors coupled as a cascade is provided between the gate of the second n-channel MOS transistor and a second differential input terminal.

Abstract: There is disclosed an inner circuit constituted of a high voltage-proof circuit section and a low voltage-proof circuit section. A usual protective circuit against a surge is directly connected to an external terminal of an IC outside the inner circuit. The high voltage-proof circuit section includes a MOS transistor driven by a power voltage VDD. The low voltage-proof circuit section includes a MOS transistor driven by a power voltage Vdd lower than the power voltage VDD. The protective circuit against the surge is individually connected to the MOS transistor driven by the power voltage Vdd. A capacitor, diode, and the like are used as the protective circuit.

Abstract: A semiconductor device having a protection circuit comprising an NPN type bipolar transistor having a collector and an emitter connected between an external connection terminal of the semiconductor device to be protected and a reference terminal, a PMOS transistor having a drain and source connected between the base and the collector of the NPN type bipolar transistor and configured to supply a base current to the base of the NPN type bipolar transistor, and a control circuit configured to supply the control signal to the gate of the PMOS transistor in response to a voltage emerging on the external connection terminal.

Abstract: A common bias section is composed of a first series circuit having an internal resistor and an external resistor connected in series and an operational amplifier having a first input terminal connected to a reference voltage, a second input terminal connected to a Vr1 node, and an output terminal connected to the series circuit. An impedance trimming section is composed of a series circuit having an internal resistor and an impedance dummy resistor connected in series, a comparator CMP having a first input terminal connected to the Vr1 node and a second input terminal connected to a Vto1 node, a code control circuit which uses a clock signal to latch an output signal from the comparator to generate a plurality of switching codes, and a switching circuit which switch a resistance value of the impedance dummy resistor.

Abstract: A semiconductor device includes an internal device, and a protection device. The internal device includes a first well region and a first semiconductor element formed in and/or on the first well. The protection device includes a second well region and a second semiconductor element formed in and/or on the second well region. The second well region has a lower impurity concentration than the first well region. The protection device protects the first semiconductor element.

Abstract: A common bias section is composed of a first series circuit having an internal resistor and an external resistor connected in series and an operational amplifier having a first input terminal connected to a reference voltage, a second input terminal connected to a Vr1 node, and an output terminal connected to the series circuit. An impedance trimming section is composed of a series circuit having an internal resistor and an impedance dummy resistor connected in series, a comparator CMP having a first input terminal connected to the Vr1 node and a second input terminal connected to a Vto1 node, a code control circuit which uses a clock signal to latch an output signal from the comparator to generate a plurality of switching codes, and a switching circuit which switch a resistance value of the impedance dummy resistor.

Abstract: An electrostatic discharge protection circuit device is disclosed, which comprises a first electrostatic discharge protection circuit connected between a first external terminal and a first ground terminal, a second electrostatic discharge protection circuit connected between a second external terminal and a second ground terminal, the second electrostatic discharge protection circuit having substantially the same configuration as that of the first electrostatic discharge protection circuit, a trigger signal line which connects to each other output nodes of surge detection circuits of the first and second electrostatic discharge protection circuits, and transfers a surge detection output of the first or second electrostatic discharge protection circuit to the other electrostatic discharge protection circuit as a trigger signal, and a common discharge line connected directly to the first ground terminal, connected to the second ground terminal via a parallel circuit composed of a forward-connected parasitic di

Abstract: A semiconductor integrated circuit system includes first and second semiconductor devices formed on a substrate and required to have properties the same as each other in operation. The first and second semiconductor devices respectively includes first and second channel regions arranged in a surface of the substrate, and first and second gate electrodes disposed on the first and second channel regions via gate insulating films. A relaxing structure is arranged to reduce fluctuations in the properties of the first and second semiconductor devices, the fluctuations being caused by the electrical effects of plasma when a plasma process is performed. The relaxing structure includes first and second short-circuiting elements respectively connected to the first and second wiring layers and equivalent to each other. The first and second short-circuiting elements are configured to short-circuit the first and second gate electrodes with the first and second channel regions, respectively.

Abstract: A semiconductor circuit system has first, second, and third external terminals electrically separated from each other. The first external terminal is configured to receive a first power supply voltage in a normal operation. A protection circuit section is provided in the circuit system and includes a rectifier to allow a surge current to pass therethrough. The rectifier has a current passage connected between a specific terminal connected to a protection target and the third external terminal. The protection circuit section further includes a first PMOS transistor configured to trigger the rectifier, based on a surge voltage inputted into the second external terminal. The first PMOS transistor has a current passage connected between the second external terminal and a base of the NPN transistor. The first PMOS transistor has a gate connected to the first external terminal.