Abstract: A gate array LSI includes a basic cell array region on which internal cell arrays are arranged, and a peripheral circuit region, arranged on the periphery of the basic cell array region. The peripheral circuit region includes input/output cell regions, for constructing an input buffer circuit and part of an output buffer circuit, and a general purpose cell array region, for constructing the remaining part of the output buffer circuit. When the output buffer circuit is not constructed, the general purpose cell array region is used for constructing various other desired circuits.

Abstract: A semiconductor integrated circuit device includes basic semiconductor elements arranged regularly in lines and rows and located at intersecting points of the lines and rows and wiring conductor layers arranged among the basic semiconductor elements regularly in lines and rows. In this semiconductor integrated circuit device, according to a desired logic operation, wiring conductor layers are cut or contact holes are formed on the wiring conductor layers to form wiring metal layers and connect the basic semiconductor elements to one another, so that an integrated circuit chip capable of performing the desired logic operation is obtained.

Abstract: Disclosed is a semiconductor device having a large number of basic cells, wherein a plurality of basic cells arranged along rows of a semiconductor substrate form a basic cell array and a plurality of the basic cell arrays are arranged along columns of the substrate, and further including spaces formed between each adjoining column. Each basic cell is comprised of first and second P-channel MIS transistors and first and second N-channel MIS transistors. The gates of both the first P-channel and the first N-channel MIS transistors form a first single common gate, and the gates of both the second P-channel and the second N-channel MIS transistors form a second single common gate. The sources or the drains of both the first P-channel and the second P-channel MIS transistors form a first single common source or drain, and the sources or the drains of both the first N-channel and the second N-channel MIS transistors form a second single common source or drain.