Abstract: A semiconductor memory including memory cells, word lines, bit lines, a row decoder, column decoder, a voltage-changing circuit, a sense amplifier, and an output circuit. Each memory cell stores multi-level data. The row decoder selects one of the word lines in accordance with an address signal. The voltage-changing circuit generates different voltages, which are applied to the row decoder. The different voltages are sequentially applied from the voltage-changing circuit to the word line selected by the row decoder. The column decoder selects a bit line every time the potential of the word line changes. The sense amplifier detects the data read from the memory cell onto the bit line every time the potential of the word line changes. The output circuit converts the data to code data.

Abstract: When an erase voltage is applied to the sources of data erasable and rewritable memory cells each having a floating gate, the erasure characteristics of the memory cells can be improved by controlling the rise time of the erase voltage or by increasing the erase voltage stepwise. In test mode, no row lines are selected by a row decoder and further the sources of the respective memory cells are set to ground level. Under these conditions, in case there exists an overerased memory cell, this cell is turned on due to depletion, so that it is possible to detect the presence of the overerased memory cell on the basis of change in potential of the column line connected to this turned on memory cell. A differential amplifier is used to detect the change in potential of the column line.

Abstract: When an erase voltage is applied to the sources of data erasable and rewritable memory cells each having a floating gate, the erasure characteristics of the memory cells can be improved by controlling the rise time of the erase voltage or by increasing the erase voltage stepwise. In test mode, no row lines are selected by a row decoder and further the sources of the respective memory cells are set to ground level. Under these conditions, in case there exists an overerased memory cell, this cell is turned on due to depletion, so that it is possible to detect the presence of the overerased memory cell on the basis of change in potential of the column line connected to this turned on memory cell. A differential amplifier is used to detect the change in potential of the column line.

Abstract: A memory system having an input buffer, an address counter, an address decoder, and a memory-cell array. Address signals are supplied to the memory-cell array. In the system, a true-address data determining section has wires or a circuit storing an internal address specific to the system. A false-data generating circuit generates false data when the internal address is in a false data area, and the false data is input to an output selecting circuit. A true-address data area detecting circuit compares the true-address data EAi with the internal address consisting of the address signals supplied from an address counter, and generates a signal REAL when the internal address is in a true-address data area. The output-selecting circuit selects the false data or the data read from the memory-cell array through a sense amplifier, in accordance with whether the signal REAL is at high level or low level. The data stored in the memory-cell array consists of true data items and false data items.

Abstract: When an erase voltage is applied to the sources of data erasable and rewritable memory cells each having a floating gate, the erasure characteristics of the memory cells can be improved by controlling the rise time of the erase voltage or by increasing the erase voltage stepwise. In test mode, no row lines are selected by a row decoder and further the sources of the respective memory cells are set to ground level. Under these conditions, in case there exists an overerased memory cell, this cell is turned on due to depletion, so that it is possible to detect the presence of the overerased memory cell on the basis of change in potential of the column line connected to this turned on memory cell. A differential amplifier is used to detect the change in potential of the column line.

Abstract: A semiconductor integrated circuit includes a chip address data designation circuit, which has nonvolatile circuit characteristics or nonvolatilely programmed wiring corresponding to a chip address assigned to each of semiconductor chips connected to common buses, to output first chip address data corresponding to the chip address upon receiving an operation power supply voltage. The semiconductor integrated circuit further includes a chip address data latch circuit for latching second chip address data supplied from outside to the semiconductor chip, and a chip selection control circuit for comparing the first chip address data and the second chip address data, and generating a chip selection signal for activating the semiconductor chip when the first chip address data and the second chip address data coincide with each other. The chip address assigned to each semiconductor chip can be stored nonvolatilely, and one of the chips can be selected in response to the chip address supplied from outside the chip.

Abstract: In a semiconductor memory apparatus having a cell array structure wherein occurrence of leak current is reduced and a margin at the time of sensing is increased, a plurality of memory transistors arranged in a matrix and having any one of four thresholds constitute banks in a column direction. The banks constitute memory cell arrays. A main bit line of Al is connected to three sub-bit lines via first selection transistors. A main ground line of Al is connected to two sub-ground lines via second selection transistors. Bank selection lines and word lines are formed to cross the main bit line and main ground line. Gates of the selection transistors are connected to the selection lines, and one selection line is connected to one selection transistor. Each of the sub-bit lines and sub-ground lines has a column of memory transistors which constitute a bank. A separation region (not shown) of a silicon oxide film, etc. is formed between the memory cell arrays to prevent leak current.

Abstract: A semiconductor memory includes memory cells, word lines, bit lines, a row decoder, column decoder, a voltage-changing circuit, a sense amplifier, and an output circuit. Each memory cell stores multi-level data. The row decoder selects one of the word lines in accordance with an address signal. The voltage-changing circuit generates different voltages, which are applied to the row decoder. The different voltages are sequentially applied from the voltage-changing circuit to the word line selected by the row decoder. The column decoder selects a bit line every time the potential of the word line changes. The sense amplifier detects the data read from the memory cell onto the bit line every time the potential of the word line changes. The output circuit converts the data to code data.

Abstract: When an erase voltage is applied to the sources of data erasable and rewritable memory cells each having a floating gate, the erasure characteristics of the memory cells can be improved by controlling the rise time of the erase voltage or by increasing the erase voltage stepwise. In test mode, no row lines are selected by a row decoder and further the sources of the respective memory cells are set to ground level. Under these conditions, in case there exists an overerased memory cell, this cell is turned on due to depletion, so that it is possible to detect the presence of the overerased memory cell on the basis of change in potential of the column line connected to this turned on memory cell. A differential amplifier is used to detect the change in potential of the column line.