Abstract: A graphic memory in which a bit of storage element is allocated to each pixel of an image to be displayed on a CRT monitor is provided. A source data transferred by a direct memory access controller is shifted by a barrel shift circuit. The resultant data and the data read from the graphic memory are subjected to an operation, and the obtained data is again stored in the graphic memory.

Abstract: The dot data to be displayed is divided and stored in an even address graphic memory and an odd address graphic memory. When data to be revised (refreshed) bridges over adjacent word units having different addresses, the CPU generates the word address of the odd address graphic memory and new dot data to be displayed. A peripheral control circuit generates the word address signal and an address signal of the adjacent address of the even address graphic memory so as to revise the dot data which bridges over two word addresses. In this way, the dot data which bridges over two addresses can be revised by only one access operation to the memory.

Abstract: A memory access apparatus in which a data memory has a plurality of data storing areas is accessed by a CPU in accordance with a sequential access method. A window latch and an adder are provided between the memory and CPU. Addresses stored in the window latch and addresses issued by the CPU are added together to create a memory access address. The window latch is so set that a data storing area within the data memory corresponding to an inputted spelling of a word is accessible by the CPU.

Abstract: A data processing apparatus for image display includes a character generator, a bit map type image memory, a CPU for accessing the character generator and the image memory to control the data stored in the image memory, a display, and a display controller for reading out the data stored in the image memory in accordance with a command from the CPU and supplying the readout data to the display. The image display apparatus further includes an image memory controller having a barrel shifter for parallelly shifting the data supplied from the CPU by a designated number of bits, a mask controller for outputting a mask data to restrict a write range of the data supplied from the CPU and a write controller for operatively combining the data from the barrel shifter and the data read from the image memory in accordance with the mask data to prepare a write data and supplying the write data to the image memory.

Abstract: An image display apparatus comprises: a computer unit for reading out dot data of an image pattern from a character generator and writing into a bit map type graphic memory; a CRT controller for reading out the dot data from this bit map type graphic memory and displaying on a CRT monitor; and a time sharing control circuit for time sharingly controlling the access from the computer unit to the bit map type graphic memory and the access from the CRT controller to this memory. The character generator is provided with a ROM which is constituted such that a dot matrix of one character pattern is segmented on a byte unit basis in the horizontal direction of raster and these segmented sub-patterns are continuously stored in this ROM in the vertical direction of raster.

Abstract: The output voltage of the drive power source for energizing the heating resistor elements on the thermal recording head, falls in response to the increase in the currents through the elements. This invention provides a thermal recording apparatus in which the time period for power supply to the elements is controlled in accordance with the number of the elements to be simultaneously energized so that the deficiency in the heat generated by each element, due to the voltage fall is obviated.