Patents by Inventor Nobuteru Oh

Nobuteru Oh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Multichip semiconductor package
    Patent number: 7501707
    Abstract: The semiconductor apparatus includes an upper semiconductor chip having an upper external terminal and a lower semiconductor chip having a lower bump for electrically connecting a lower external terminal and the upper external terminal. The circuit surfaces of the upper semiconductor chip and the lower semiconductor chip are electrically connected to each other via the bump. A low impedance line having lower impedance than the internal line of the lower semiconductor chip is formed on top of the lower semiconductor chip for electrically connecting the lower external terminal and the bump.
    Type: Grant
    Filed: March 7, 2005
    Date of Patent: March 10, 2009
    Assignee: NEC Electronics Corporation
    Inventors: Yoshiaki Morishita, Nobuteru Oh
  • Integrated circuit device with multiple chips in one package
    Patent number: 7400134
    Abstract: The integrated circuit device includes a memory chip and a logic chip. The memory chip has memory I/O pads and test pads. The test pads are placed in line at the position outer than memory I/O pads and larger than the memory I/O pads. The logic chip has logic COC I/O pads. The logic COC I/O pads are connected to the memory I/O pads.
    Type: Grant
    Filed: January 19, 2005
    Date of Patent: July 15, 2008
    Assignee: NEC Electronics Corporation
    Inventors: Yoshiaki Morishita, Nobuteru Oh, Tomoaki Isozaki
  • Semiconductor apparatus and method for manufacturing semiconductor apparatus
    Publication number: 20050199994
    Abstract: The semiconductor apparatus includes an upper semiconductor chip having an upper external terminal and a lower semiconductor chip having a lower bump for electrically connecting a lower external terminal and the upper external terminal. The circuit surfaces of the upper semiconductor chip and the lower semiconductor chip are electrically connected to each other via the bump. A low impedance line having lower impedance than the internal line of the lower semiconductor chip is formed on top of the lower semiconductor chip for electrically connecting the lower external terminal and the bump.
    Type: Application
    Filed: March 7, 2005
    Publication date: September 15, 2005
    Inventors: Yoshiaki Morishita, Nobuteru Oh
  • Integrated circuit device
    Publication number: 20050156616
    Abstract: The integrated circuit device includes a memory chip and a logic chip. The memory chip has memory I/O pads and test pads. The test pads are placed in line at the position outer than memory I/O pads and larger than the memory I/O pads. The logic chip has logic COC I/O pads. The logic COC I/O pads are connected to the memory I/O pads.
    Type: Application
    Filed: January 19, 2005
    Publication date: July 21, 2005
    Inventors: Yoshiaki Morishita, Nobuteru Oh, Tomoaki Isozaki
  • Flip-chip semiconductor device having I/O modules in an internal circuit area
    Patent number: 6858924
    Abstract: A semiconductor device includes an internal circuit area including a plurality of I/O modules, and a peripheral area receiving therein a pair of loop test lines for testing I/O buffers in the I/O modules. The internal test line extending from each of the loop test lines toward the internal circuit area includes an out-module test line formed as the topmost layer, a first in-module test line formed as the topmost layer and connected to the out-module test line, and a second in-module test line, a portion of which is formed by connecting the in-buffer test lines together.
    Type: Grant
    Filed: May 27, 2003
    Date of Patent: February 22, 2005
    Assignee: NEC Electronics Corporation
    Inventors: Yoshihiro Masumura, Nobuteru Oh, Hiroyuki Furukawa
  • Flip-chip semiconductor device having I/O modules in an internal circuit area
    Publication number: 20030222355
    Abstract: A semiconductor device includes an internal circuit area including a plurality of I/O modules, and a peripheral area receiving therein a pair of loop test lines for testing I/O buffers in the I/O modules. The internal test line extending from each of the loop test lines toward the internal circuit area includes an out-module test line formed as the topmost layer, a first in-module test line formed as the topmost layer and connected to the out-module test line, and a second in-module test line, a portion of which is formed by connecting the in-buffer test lines together.
    Type: Application
    Filed: May 27, 2003
    Publication date: December 4, 2003
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Yoshihiro Masumura, Nobuteru Oh, Hiroyuki Furukawa