Patents by Inventor Nobuya Koike
Nobuya Koike has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10453946Abstract: A semiconductor device and an electronic device are improved in performances by supporting a large current. An emitter terminal protrudes from a first side of a sealing body, and signal terminals protrude from a second sides of the sealing body. Namely, the side of the sealing body from which the emitter terminal protrudes and the side of the sealing body from which the signal terminals protrude are different. More particularly, the signal terminals protrude from the side of the sealing body opposite the side thereof from which the emitter terminal protrudes. Further, a second semiconductor chip including a diode formed therein is mounted over a first surface of a chip mounting portion in such a manner as to be situated between the emitter terminal and the a first semiconductor chip including an IGBT formed therein in plan view.Type: GrantFiled: May 11, 2018Date of Patent: October 22, 2019Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Akira Muto, Nobuya Koike, Masaki Kotsuji, Yukihiro Narita
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Publication number: 20180261690Abstract: A semiconductor device and an electronic device are improved in performances by supporting a large current. An emitter terminal protrudes from a first side of a sealing body, and signal terminals protrude from a second sides of the sealing body. Namely, the side of the sealing body from which the emitter terminal protrudes and the side of the sealing body from which the signal terminals protrude are different. More particularly, the signal terminals protrude from the side of the sealing body opposite the side thereof from which the emitter terminal protrudes. Further, a second semiconductor chip including a diode formed therein is mounted over a first surface of a chip mounting portion in such a manner as to be situated between the emitter terminal and the a first semiconductor chip including an IGBT formed therein in plan view.Type: ApplicationFiled: May 11, 2018Publication date: September 13, 2018Inventors: Akira Muto, Nobuya Koike, Masaki Kotsuji, Yukihiro Narita
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Patent number: 10031164Abstract: A power MOSFET and a sense MOSFET for detecting a current of the power MOSFET are formed in a semiconductor chip, and a source pad and a Kelvin pad are formed of a source electrode for the power MOSFET. The source pad is a pad for outputting the current flowing to the power MOSFET, and the Kelvin pad is a pad for detecting a source potential of the power MOSFET. The source electrode has a slit, and at least a part of the slit is arranged between the source pad and the Kelvin pad when seen in a plan view.Type: GrantFiled: September 21, 2016Date of Patent: July 24, 2018Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Keita Takada, Nobuya Koike, Akihiro Nakahara, Makoto Tanaka
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Patent number: 9997620Abstract: A semiconductor device and an electronic device are improved in performances by supporting a large current. An emitter terminal protrudes from a first side of a sealing body, and signal terminals protrude from a second sides of the sealing body. Namely, the side of the sealing body from which the emitter terminal protrudes and the side of the sealing body from which the signal terminals protrude are different. More particularly, the signal terminals protrude from the side of the sealing body opposite the side thereof from which the emitter terminal protrudes. Further, a second semiconductor chip including a diode formed therein is mounted over a first surface of a chip mounting portion in such a manner as to be situated between the emitter terminal and the a first semiconductor chip including an IGBT formed therein in plan view.Type: GrantFiled: June 13, 2017Date of Patent: June 12, 2018Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Akira Muto, Nobuya Koike, Masaki Kotsuji, Yukihiro Narita
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Publication number: 20170287818Abstract: A semiconductor device and an electronic device are improved in performances by supporting a large current. An emitter terminal protrudes from a first side of a sealing body, and signal terminals protrude from a second sides of the sealing body. Namely, the side of the sealing body from which the emitter terminal protrudes and the side of the sealing body from which the signal terminals protrude are different. More particularly, the signal terminals protrude from the side of the sealing body opposite the side thereof from which the emitter terminal protrudes. Further, a second semiconductor chip including a diode formed therein is mounted over a first surface of a chip mounting portion in such a manner as to be situated between the emitter terminal and the a first semiconductor chip including an IGBT formed therein in plan view.Type: ApplicationFiled: June 13, 2017Publication date: October 5, 2017Inventors: Akira Muto, Nobuya Koike, Masaki Kotsuji, Yukihiro Narita
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Patent number: 9704979Abstract: A semiconductor device and an electronic device are improved in performances by supporting a large current. An emitter terminal protrudes from a first side of a sealing body, and signal terminals protrude from a second sides of the sealing body. Namely, the side of the sealing body from which the emitter terminal protrudes and the side of the sealing body from which the signal terminals protrude are different. More particularly, the signal terminals protrude from the side of the sealing body opposite the side thereof from which the emitter terminal protrudes. Further, a second semiconductor chip including a diode formed therein is mounted over a first surface of a chip mounting portion in such a manner as to be situated between the emitter terminal and the a first semiconductor chip including an IGBT formed therein in plan view.Type: GrantFiled: May 26, 2014Date of Patent: July 11, 2017Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Akira Muto, Nobuya Koike, Masaki Kotsuji, Yukihiro Narita
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Patent number: 9396971Abstract: There is provided a technology enabling the improvement of the reliability of a semiconductor device manufactured by physically fixing separately formed chip mounting portion and lead frame. A feature of an embodiment resides in that, a second junction portion formed in a suspension lead is fitted into a first junction portion formed in a chip mounting portion, thereby to physically fix the chip mounting portion and the suspension lead. Specifically, the first junction portion is formed of a concave part disposed in the surface of the chip mounting portion. The second junction portion forms a part of the suspension lead.Type: GrantFiled: July 21, 2015Date of Patent: July 19, 2016Assignee: Renesas Electronics CorporationInventors: Yukihiro Sato, Nobuya Koike
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Patent number: 9230831Abstract: There is provided a technology enabling the improvement of the reliability of a semiconductor device manufactured by physically fixing separately formed chip mounting portion and lead frame. A feature of an embodiment resides in that, a second junction portion formed in a suspension lead is fitted into a first junction portion formed in a chip mounting portion, thereby to physically fix the chip mounting portion and the suspension lead. Specifically, the first junction portion is formed of a concave part disposed in the surface of the chip mounting portion. The second junction portion forms a part of the suspension lead.Type: GrantFiled: February 3, 2015Date of Patent: January 5, 2016Assignee: Renesas Electronics CorporationInventors: Yukihiro Sato, Nobuya Koike
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Patent number: 9129979Abstract: It is made for the layout of the mounting wiring at the time of mounting to become efficient by changing the structure of a semiconductor device. A first chip is mounted on a first die pad, and a second chip is also mounted on a second die pad. A first die pad and a second die pad do division structure in parallel to the first side and second side of sealing body 40. As a result, the pin for an output from a first chip and the pin for control of the circuit for a drive can make it able to project from a counter direction, and can set the wiring layout at the time of mounting as the minimum route.Type: GrantFiled: June 26, 2012Date of Patent: September 8, 2015Assignee: Renesas Electronics CorporationInventors: Nobuya Koike, Atsushi Fujiki, Norio Kido, Yukihiro Sato, Hiroyuki Nakamura
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Patent number: 9024423Abstract: A semiconductor chip in which a power MOSFET is placed above a semiconductor chip in which another power MOSFET is formed and they are sealed with an encapsulation resin. The semiconductor chips are so arranged that the upper semiconductor chip does not overlap with a gate pad electrode of the lower semiconductor chip in a plan view. The semiconductor chips are identical in size and the respective source pad electrodes and gate pad electrodes of the lower semiconductor chip and the upper semiconductor chip are identical in shape and arrangement. The lower semiconductor chip and the upper semiconductor chip are arranged with their respective centers displaced from each other. Accordingly, the size of a semiconductor device can be reduced.Type: GrantFiled: April 26, 2010Date of Patent: May 5, 2015Assignee: Renesas Electronics CorporationInventors: Akira Muto, Yuichi Machida, Nobuya Koike, Atsushi Fujiki, Masaki Tamura
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Patent number: 8994159Abstract: To prevent, in a resin-sealed type semiconductor package, generation of cracks in a die bonding material used for mounting of a semiconductor chip. A semiconductor chip is mounted over the upper surface of a die pad via a die bonding material, followed by sealing with an insulating resin. The top surface of the die pad to be brought into contact with the insulating resin is surface-roughened, while the bottom surface of the die pad and an outer lead portion are not surface-roughened.Type: GrantFiled: January 14, 2013Date of Patent: March 31, 2015Assignee: Renesas Electronics CorporationInventors: Hiroyuki Nakamura, Akira Muto, Nobuya Koike, Atsushi Nishikizawa, Yukihiro Sato, Katsuhiko Funatsu
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Patent number: 8975733Abstract: There is provided a technology enabling the improvement of the reliability of a semiconductor device manufactured by physically fixing separately formed chip mounting portion and lead frame. A feature of an embodiment resides in that, a second junction portion formed in a suspension lead is fitted into a first junction portion formed in a chip mounting portion, thereby to physically fix the chip mounting portion and the suspension lead. Specifically, the first junction portion is formed of a concave part disposed in the surface of the chip mounting portion. The second junction portion forms a part of the suspension lead.Type: GrantFiled: February 20, 2013Date of Patent: March 10, 2015Assignee: Renesas Electronics CorporationInventors: Yukihiro Sato, Nobuya Koike
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Publication number: 20140367739Abstract: A semiconductor device and an electronic device are improved in performances by supporting a large current. An emitter terminal protrudes from a first side of a sealing body, and signal terminals protrude from a second sides of the sealing body. Namely, the side of the sealing body from which the emitter terminal protrudes and the side of the sealing body from which the signal terminals protrude are different. More particularly, the signal terminals protrude from the side of the sealing body opposite the side thereof from which the emitter terminal protrudes. Further, a second semiconductor chip including a diode formed therein is mounted over a first surface of a chip mounting portion in such a manner as to be situated between the emitter terminal and the a first semiconductor chip including an IGBT formed therein in plan view.Type: ApplicationFiled: May 26, 2014Publication date: December 18, 2014Applicant: Renesas Electronics CorporationInventors: Akira Muto, Nobuya Koike, Masaki Kotsuji, Yukihiro Narita
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Patent number: 8564112Abstract: To improve the performance and reliability of semiconductor devices. For the semiconductor chip CP1, power MOSFETs Q1 and Q2 for the switch, a diode DD1 for detecting the heat generation of the power MOSFET Q1, a diode DD2 for detecting the heat generation of the power MOSFET Q2, and plural pad electrodes PD are formed. The power MOSFET Q1 and the diode DD1 are arranged in a first MOSFET region RG1 on the side of a side SD1, and the power MOSFET Q2 and the diode DD2 are arranged in a second MOSFET region RG2 on the side of a side SD2. The diode DD1 is arranged along the side SD1, the diode DD2 is arranged along the side SD2, and all pad electrodes PD other than the pad electrodes PDS1 and PDS2 for the source are arranged along a side SD3 between the diodes DD1 and DD2.Type: GrantFiled: October 19, 2012Date of Patent: October 22, 2013Assignee: Renesas Electronics CorporationInventors: Hiroyuki Nakamura, Atsushi Fujiki, Tatsuhiro Seki, Nobuya Koike, Yukihiro Sato, Kisho Ashida
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Publication number: 20130256860Abstract: There is provided a technology enabling the improvement of the reliability of a semiconductor device manufactured by physically fixing separately formed chip mounting portion and lead frame. A feature of an embodiment resides in that, a second junction portion formed in a suspension lead is fitted into a first junction portion formed in a chip mounting portion, thereby to physically fix the chip mounting portion and the suspension lead. Specifically, the first junction portion is formed of a concave part disposed in the surface of the chip mounting portion. The second junction portion forms a part of the suspension lead.Type: ApplicationFiled: February 20, 2013Publication date: October 3, 2013Inventors: Yukihiro Sato, Nobuya Koike
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Patent number: 8367479Abstract: To prevent, in a resin-sealed type semiconductor package, generation of cracks in a die bonding material used for mounting of a semiconductor chip. A semiconductor chip is mounted over the upper surface of a die pad via a die bonding material, followed by sealing with an insulating resin. The top surface of the die pad to be brought into contact with the insulating resin is surface-roughened, while the bottom surface of the die pad and an outer lead portion are not surface-roughened.Type: GrantFiled: March 5, 2010Date of Patent: February 5, 2013Assignee: Renesas Electronics CorporationInventors: Hiroyuki Nakamura, Akira Muto, Nobuya Koike, Atsushi Nishikizawa, Yukihiro Sato, Katsuhiko Funatsu
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Patent number: 8362626Abstract: An SiP (semiconductor device) using a stacked packaging method for stacking a microcomputer IC chip over a driver IC chip in which circuits sensitive to heat or noise, including an analog to digital conversion circuit, a digital to analog conversion circuit, a sense amplifier circuit of a memory (RAM or ROM), or a power supply circuit of a microcomputer IC chip, are prevented from two-dimensionally overlapping with a driver circuit of the lower-side driver IC chip to reduce, during the operation, the effect of heat or noise, which the circuits sensitive to heat or noise of the microcomputer IC chip receive from the driver circuit of the lower-side driver IC chip, thereby improving the operation stability of the SiP (semiconductor device) using the stacked packaging method.Type: GrantFiled: August 25, 2008Date of Patent: January 29, 2013Assignee: Renesas Electronics CorporationInventors: Nobuya Koike, Shinya Nagata
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Patent number: 8338927Abstract: The semiconductor device includes a semiconductor chip, a chip mounting portion, a suspension lead, and a plurality of leads. Each of the plurality of leads has a first part and a second part, and the suspension lead has a first part and a second part. The first part of each of the plurality of leads and the suspension lead project from the plurality of side surfaces of the sealing body, respectively. Parts of the side surfaces of the plurality of leads and the suspension lead are exposed from the plurality of side surfaces of the sealing body, respectively. An area of the obverse surface of the first part of the suspension lead is larger than an area of the obverse surface of the first part of each of the plurality of leads in a plan view.Type: GrantFiled: September 6, 2011Date of Patent: December 25, 2012Assignee: Renesas Electronics CorporationInventors: Hiroyuki Nakamura, Atsushi Nishikizawa, Nobuya Koike
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Patent number: 8299599Abstract: To improve the performance and reliability of semiconductor devices. For the semiconductor chip CP1, power MOSFETs Q1 and Q2 for the switch, a diode DD1 for detecting the heat generation of the power MOSFET Q1, a diode DD2 for detecting the heat generation of the power MOSFET Q2, and plural pad electrodes PD are formed. The power MOSFET Q1 and the diode DD1 are arranged in a first MOSFET region RG1 on the side of a side SD1, and the power MOSFET Q2 and the diode DD2 are arranged in a second MOSFET region RG2 on the side of a side SD2. The diode DD1 is arranged along the side SD1, the diode DD2 is arranged along the side SD2, and all pad electrodes PD other than the pad electrodes PDS1 and PDS2 for the source are arranged along a side SD3 between the diodes DD1 and DD2.Type: GrantFiled: March 3, 2011Date of Patent: October 30, 2012Assignee: Renesas Electronics CorporationInventors: Hiroyuki Nakamura, Atsushi Fujiki, Tatsuhiro Seki, Nobuya Koike, Yukihiro Sato, Kisho Ashida
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Patent number: 8298859Abstract: There is a need for providing a technology capable of decreasing on-resistance of a power transistor in a semiconductor device that integrates the power transistor and a control integrated circuit into a single semiconductor chip. There is another need for providing a technology capable of reducing a chip size of a semiconductor device. A semiconductor chip includes a power transistor formation region to form a power transistor, a logic circuit formation region to form a logic circuit, and an analog circuit formation region to form an analog circuit. A pad is formed in the power transistor formation region. The pad and a lead are connected through a clip whose cross section is larger than that of a wire. On the other hand, a bonding pad is connected through the wire.Type: GrantFiled: February 25, 2011Date of Patent: October 30, 2012Assignee: Renesas Electronics CorporationInventors: Nobuya Koike, Tsukasa Matsushita, Hiroshi Sato, Keiichi Okawa, Atsushi Nishikizawa