Abstract: Disclosed is a decoder, receiving the first and the second reference voltage groups and selecting a reference voltage in accordance with a received digital signal, including a first sub-decoder receiving the first reference voltage group, a second sub-decoder receiving the second reference voltage group 20B, and a third sub-decoder receiving a reference voltage selected by the second sub-decoder and outputting the selected reference voltage to the first sub-decoder or an output terminal of the decoder. The first sub-decoder includes a transistor of a first conductivity type having a back gate supplied with a first power supply voltage, the second sub-decoder includes a transistor of the first conductivity type having a back gate supplied with a second power supply voltage, and the third sub-decoder includes a transistor of the first conductivity type having a back gate supplied with a first power supply voltage.

Abstract: A display panel drive apparatus is provided with: a drive circuit outputting drive voltages to a display panel in response to a timing control signal used for timing control of image display on the display panel; and a booster circuit feeding a boosted power supply voltage to the drive circuit. The booster circuit includes a charge pump circuit generating the boosted power supply voltage by boosting an input power supply voltage in response to a boosting clock; and a pulse skip circuit monitoring a voltage level of the boosted power supply voltage and controlling an boosting operation of the charge pump circuit in response to the voltage level of the boosted power supply voltage. The pulse skip circuit is configured to allow the charge pump circuit to initiate the boosting operation in synchronization with the timing control signal.

Abstract: Disclosed is a decoder, receiving the first and the second reference voltage groups and selecting a reference voltage in accordance with a received digital signal, including a first sub-decoder receiving the first reference voltage group, a second sub-decoder receiving the second reference voltage group 20B, and a third sub-decoder receiving a reference voltage selected by the second sub-decoder and outputting the selected reference voltage to the first sub-decoder or an output terminal of the decoder. The first sub-decoder includes a transistor of a first conductivity type having a back gate supplied with a first power supply voltage, the second sub-decoder includes a transistor of the first conductivity type having a back gate supplied with a second power supply voltage, and the third sub-decoder includes a transistor of the first conductivity type having a back gate supplied with a first power supply voltage.

Abstract: A display panel drive apparatus is provided with: a drive circuit outputting drive voltages to a display panel in response to a timing control signal used for timing control of image display on the display panel; and a booster circuit feeding a boosted power supply voltage to the drive circuit. The booster circuit includes a charge pump circuit generating the boosted power supply voltage by boosting an input power supply voltage in response to a boosting clock; and a pulse skip circuit monitoring a voltage level of the boosted power supply voltage and controlling an boosting operation of the charge pump circuit in response to the voltage level of the boosted power supply voltage. The pulse skip circuit is configured to allow the charge pump circuit to initiate the boosting operation in synchronization with the timing control signal.

Abstract: An integrated circuit device includes a first memory unit and a conversion part for converting the parallel data read from the first memory unit into serial data. The integrated circuit device also includes a second memory unit that can write and read the data indicating the order of reading the parallel data from the first memory unit and the order of converting the parallel data into the serial data.